The mpic is either the main interrupt controller or sits behind a GIC. But there is no way that both variants are available on the same system.
Share the cpu hotplug state. Signed-off-by: Thomas Gleixner <[email protected]> Cc: Thomas Petazzoni <[email protected]> Cc: Marc Zyngier <[email protected]> --- drivers/irqchip/irq-armada-370-xp.c | 2 +- include/linux/cpuhotplug.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -583,7 +583,7 @@ static int __init armada_370_xp_mpic_of_ #endif } else { #ifdef CONFIG_SMP - cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_CASC_STARTING, + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING, "irqchip/armada/cascade:starting", mpic_cascaded_starting_cpu, NULL); #endif --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -82,7 +82,6 @@ enum cpuhp_state { CPUHP_AP_IRQ_GIC_STARTING, CPUHP_AP_IRQ_HIP04_STARTING, CPUHP_AP_IRQ_ARMADA_XP_STARTING, - CPUHP_AP_IRQ_ARMADA_CASC_STARTING, CPUHP_AP_IRQ_BCM2836_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY, CPUHP_AP_PERF_X86_UNCORE_STARTING,
