> Quoting Eric W. Biederman <[EMAIL PROTECTED]>: > Subject: Re: SATA resume slowness, e1000 MSI warning > > "Michael S. Tsirkin" <[EMAIL PROTECTED]> writes: > > > OK I guess. I gather we assume writing read-only registers has no side > > effects? > > Are there rumors circulating wrt to these? > > I haven't heard anything about that, and if we are writing the same value back > it should be pretty safe. > > I have heard it asserted that at least one version of the pci spec > only required 32bit accesses to be supported by the hardware. One of > these days I will have to look that and see if it is true.
Maybe. But surely before the PCI-X days. > I do know > it can be weird for hardware developers to support multiple kinds of > decode. Is this the only place where Linux uses pci_read_config_word/pci_read_config_dword? I think such hardware will be pretty much DOA on all OS-es. Why don't we wait and see whether someone reports a broken config? > As I recall for pci and pci-x at the hardware level the only > difference in between 32bit transactions and smaller ones is the state > of the byte-enable lines. True, and same holds for PCI-Express. So let's assume hardware implements RO correctly but ignores the BE bits - nothing bad happens then, right? -- MST - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
