On 01/18, Eric Anholt wrote: > Our core PLLs are intended to be configured once and left alone. With > the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would > change PLLD just to get closer to the requested DSI clock, thus > changing PLLD_PER, the UART and ethernet PHY clock rates downstream of > it, and breaking ethernet. > > We *do* want PLLH to change so that PLLH_AUX can be exactly the value > we want, though. Thus, we need to have a per-divider policy of > whether to pass rate changes up. > > Signed-off-by: Eric Anholt <[email protected]> > ---
Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
