On Fri, 2017-01-27 at 10:02 -0800, Tyrel Datwyler wrote: > > The problem is that we are packing an in-memory structure into 2 > > registers and it's expected that this structure is laid out in the > > registers as if it had been loaded by a BE CPU. > > This is only the case if the cpu is BE. If the cpu is LE, regardless of > the fact that our in memory structure is laid out BE, when we break it > into 2 words each of those words needs to be loaded LE.
That doesn't make sense and doesn't match the code... The structure needs to always have the same in-register layout regardless of the endianness of the CPU, especially since the underlying hypervisor will most likely be BE :-) Thta's why the code does a be64_to_cpu() when loading it, this in effect performs a "BE" load, which on a BE CPU is just a normal load and on LE is a swap to compensate for the CPU loading it the "wrong way around". Cheers, Ben.