On Wed, Jan 25, 2017 at 07:51:54PM +0100, Paul Cercueil wrote: > This commit adds documentation for the devicetree bidings of the > pinctrl-ingenic driver, which handles pin configuration and pin > muxing of the Ingenic SoCs currently supported by the Linux kernel. > > Signed-off-by: Paul Cercueil <p...@crapouillou.net> > --- > .../bindings/pinctrl/ingenic,pinctrl.txt | 77 > ++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt > > v2: Rewrote the documentation for the new pinctrl-ingenic driver > v3: No changes > > diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt > b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt > new file mode 100644 > index 000000000000..ead5b01ad471 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt > @@ -0,0 +1,77 @@ > +Ingenic jz47xx pin controller > + > +Please refer to pinctrl-bindings.txt in this directory for details of the > +common pinctrl bindings used by client devices, including the meaning of the > +phrase "pin configuration node". > + > +For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins > may > +be used as GPIOs, multiplexed device functions are configured within the > +GPIO port configuration registers and it is typical to refer to pins using > the > +naming scheme "PxN" where x is a character identifying the GPIO port with > +which the pin is associated and N is an integer from 0 to 31 identifying the > +pin within that GPIO port. For example PA0 is the first pin in GPIO port A, > and > +PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to > +PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for > a > +total of 192 pins.
>From the overlapping register addresses in the examples and this description, it looks like the pinctrlr and gpio controller are 1 block. If so, then there should only be 1 node. Rob
