On Wed, Feb 01, 2017 at 11:25:07PM +0100, Borislav Petkov wrote: > On Wed, Feb 01, 2017 at 09:55:44PM +0000, Ghannam, Yazen wrote: > > Okay, in that case I would prefer to define a synthetic bit. I think it'll > > be a lot > > more clear. > > No need - it is ok this way too. Now let me apply your changes ontop. > I'd like to have two separate patches for this.
Ok, here are your changes ontop of the first patch. We can still avoid the division on SMT-off systems. More playing with this tomorrow. It is late here and brain wants to sleep now. --- >From 4b3b9626ef8a535df304aaa017b61436a3b37922 Mon Sep 17 00:00:00 2001 From: Yazen Ghannam <[email protected]> Date: Wed, 1 Feb 2017 23:33:16 +0100 Subject: [PATCH] x86/CPU/AMD: Fix Zen SMT topology After a33d331761bc ("x86/CPU/AMD: Fix Bulldozer topology"), SMT scheduling topology for Fam17h systems is broken because the ThreadId is included in the ApicId when SMT is enabled. So, without further decoding cpu_core_id is unique for each thread rather than the same for threads on the same core. This didn't affect systems with SMT disabled. Make cpu_core_id be what it is defined to be. Signed-off-by: Yazen Ghannam <[email protected]> Signed-off-by: Borislav Petkov <[email protected]> --- arch/x86/kernel/cpu/amd.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e7158afb322b..349b7d9baf3f 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -319,6 +319,13 @@ static void amd_get_topology(struct cpuinfo_x86 *c) if (c->x86 == 0x15) c->cu_id = ebx & 0xff; + if (c->x86 >= 0x17) { + c->cpu_core_id = ebx & 0xff; + + if (smp_num_siblings > 1) + c->x86_max_cores /= smp_num_siblings; + } + /* * We may have multiple LLCs if L3 caches exist, so check if we * have an L3 cache by looking at the L3 cache CPUID leaf. -- 2.11.0 -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
