On Thu, Feb 2, 2017 at 4:05 PM, <thor.tha...@linux.intel.com> wrote: > From: Thor Thayer <thor.tha...@linux.intel.com> > > Add the device tree entries needed to support the EMAC AXI > bus settings on the Arria10 SoCFPGA chip. > > Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> > --- > v2 Add the AXI configuration to the other DW EMACs in the chip. > --- > arch/arm/boot/dts/socfpga_arria10.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) >
Applied! Thanks, Dinh
