On Wed, 2017-02-15 at 13:47 +0800, yuantian.t...@nxp.com wrote: > From: Tang Yuantian <yuantian.t...@nxp.com> > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will be > used for the core PLLs. > > Signed-off-by: Scott Wood <o...@buserror.net> > Signed-off-by: Tang Yuantian <yuantian.t...@nxp.com> > --- > drivers/clk/clk-qoriq.c | 91 +++++++++++++++++++++++++++++++++++++++++-----
Why did you reset the author on these patches? Have you changed anything? Why aren't they marked either v2 or resend? -Scott
