On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: > The L3 cache PMU use N-N SPI interrupt which has no support > in kernel mainline.
Could you elaborate on what you mean by this? I don't understand what is meant here. How exactly are the interrupts wired up in HW, and what exactly is not supported by Linux? > So use hrtimer to poll and update event > counter to avoid overflow condition for L3 cache PMU. > A interval of 10 seconds is used for the hrtimer. > The time interval can be configured in the sysfs. I'm not too keen on giving userspace the ability to control this, since it gives an awful lot of rope for userspace to tie around itself. Thanks, Mark.
