On Thu, Feb 23, 2017 at 09:20:06AM +0100, Mike Galbraith wrote: > On Thu, 2017-02-09 at 16:07 +0100, Thomas Gleixner wrote:
> > Can you share your cheatery ? > > I can do better than that... sorta ;-) > > x86/tsc: Fix unreliable tsc adjust > > On a 4 socket BIOS challenged box (4x18), the magic number '3' does > not work reliably, resulting in TSC being disabled more often than not. > > Replace defective magic number '3' with functional magic number '5', > derived via scientific method number sockets in afflicted box, plus > one for good luck, and reboot box a lot to validate (poke 'n' hope). > > Signed-off-by: Mike Galbraith <[email protected]> > --- > arch/x86/kernel/tsc_sync.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > --- a/arch/x86/kernel/tsc_sync.c > +++ b/arch/x86/kernel/tsc_sync.c > @@ -294,7 +294,7 @@ void check_tsc_sync_source(int cpu) > if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST)) > atomic_set(&test_runs, 1); > else > - atomic_set(&test_runs, 3); > + atomic_set(&test_runs, 5); > retry: > /* > * Wait for the target to start or to skip the test: Confirmed on another box too; the default of 3 wasn't sufficient to achieve sync. When upping it to 16, sync was achieved in around 4 runs or so.
