On Wed, 22 Feb 2017, Liang, Kan wrote: > > So from what I understand, the issue is if we have an architecture with > > full- > > width counters and we trigger a x86_perf_event_update() when bit > > 47 is set? > > No. It related to the counter width. The number of bits we can use should be > 1 bit less than the total width. Otherwise, there will be problem. > For big cores such as haswell, broadwell, skylake, the counter width is 48 > bit. > So we can only use 47 bits. > For Silvermont and KNL, the counter width is only 32 bit I think. So we can > only > use 31 bits.
So on a machine with 48-bit counters I should just have a counting event that counts to somewhere above 0x8000 0000 0001 and it should show problems? Because I am unable to trigger this. But I guess if anywhere along the line x86_perf_event_update() is run then you start over? I noticed your original reproducer bound the event to a core, is that needed to trigger this? Can it happen on a fixed event or only a genearl purpose event? > > So if I have a test that runs in a loop for 2^48 retired instructions (which > > takes ~12 hours on a recent machine) and then reads the results, they > > might be wrong? > > It only needs several minutes to reproduce the issue on SLM/KNL. Yes, but I only have machines with 48-bit counters. So it's going to take 256 times as long as on a machine with 40-bit counters. I have an assembly loop that can consistently generate 2 instructions/cycle (I'd be glad to hear suggestions for events that count faster) and on a broadwell-ep machine it still takes at least 7 hours or so to get up to 0x800000000000. Vince
