Commit-ID: ab6d9468631a6e56e4c071c6ce6710956485fe08 Gitweb: http://git.kernel.org/tip/ab6d9468631a6e56e4c071c6ce6710956485fe08 Author: Kyle Huey <m...@kylehuey.com> AuthorDate: Mon, 20 Mar 2017 01:16:19 -0700 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Mon, 20 Mar 2017 16:10:32 +0100
x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES This matches the only public Intel documentation of this MSR, in the "Virtualization Technology FlexMigration Application Note" (preserved at https://bugzilla.kernel.org/attachment.cgi?id=243991) Signed-off-by: Kyle Huey <kh...@kylehuey.com> Cc: Grzegorz Andrejczuk <grzegorz.andrejc...@intel.com> Cc: k...@vger.kernel.org Cc: Radim Krčmář <rkrc...@redhat.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Dave Hansen <dave.han...@linux.intel.com> Cc: Andi Kleen <a...@firstfloor.org> Cc: linux-kselft...@vger.kernel.org Cc: Nadav Amit <nadav.a...@gmail.com> Cc: Robert O'Callahan <rob...@ocallahan.org> Cc: Richard Weinberger <rich...@nod.at> Cc: "Rafael J. Wysocki" <rafael.j.wyso...@intel.com> Cc: Borislav Petkov <b...@suse.de> Cc: Andy Lutomirski <l...@kernel.org> Cc: Len Brown <len.br...@intel.com> Cc: Shuah Khan <sh...@kernel.org> Cc: user-mode-linux-de...@lists.sourceforge.net Cc: Jeff Dike <jd...@addtoit.com> Cc: Alexander Viro <v...@zeniv.linux.org.uk> Cc: user-mode-linux-u...@lists.sourceforge.net Cc: David Matlack <dmatl...@google.com> Cc: Boris Ostrovsky <boris.ostrov...@oracle.com> Cc: Dmitry Safonov <dsafo...@virtuozzo.com> Cc: linux-fsde...@vger.kernel.org Cc: Paolo Bonzini <pbonz...@redhat.com> Link: http://lkml.kernel.org/r/20170320081628.18952-2-kh...@kylehuey.com Signed-off-by: Thomas Gleixner <t...@linutronix.de> --- arch/x86/include/asm/msr-index.h | 6 +++--- arch/x86/kernel/cpu/intel.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4c928f3..f429b70 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -553,10 +553,10 @@ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) -/* MISC_FEATURE_ENABLES non-architectural features */ -#define MSR_MISC_FEATURE_ENABLES 0x00000140 +/* MISC_FEATURES_ENABLES non-architectural features */ +#define MSR_MISC_FEATURES_ENABLES 0x00000140 -#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1 +#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 #define MSR_IA32_TSC_DEADLINE 0x000006E0 diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 0631977..e229318 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -91,13 +91,13 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) } if (ring3mwait_disabled) { - msr_clear_bit(MSR_MISC_FEATURE_ENABLES, - MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); + msr_clear_bit(MSR_MISC_FEATURES_ENABLES, + MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); return; } - msr_set_bit(MSR_MISC_FEATURE_ENABLES, - MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); + msr_set_bit(MSR_MISC_FEATURES_ENABLES, + MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
