On Wed, 22 Mar 2017 20:34:17 +0530 "Gautham R. Shenoy" <e...@linux.vnet.ibm.com> wrote:
> From: "Gautham R. Shenoy" <e...@linux.vnet.ibm.com> > > POWER9 DD1.0 hardware has an issue due to which the SPRs of a thread > waking up from stop 0,1,2 with ESL=1 can endup being misplaced in the > core. Thus the HSPRG0 of a thread waking up from can contain the paca > pointer of its sibling. > > This patch implements a context recovery framework within threads of a > core, by provisioning space in paca_struct for saving every sibling > threads's paca pointers. Basically, we should be able to arrive at the > right paca pointer from any of the thread's existing paca pointer. > > At bootup, during powernv idle-init, we save the paca address of every > CPU in each one its siblings paca_struct in the slot corresponding to > this CPU's index in the core. > > On wakeup from a stop, the thread will determine its index in the core > from the TIR register and recover its PACA pointer by indexing into > the correct slot in the provisioned space in the current PACA. > > Furthermore, ensure that the NVGPRs are restored from the stack on the > way out by setting the NAPSTATELOST in paca. > > [Changelog written with inputs from sva...@linux.vnet.ibm.com] Looks good. Reviewed-by: Nicholas Piggin <npig...@gmail.com>
