PCI configuration space should be mapped with a memory region type that
generates on the CPU host bus non-posted write transations. Update the
driver to use the devm_ioremap_nopost* interface to make sure the correct
memory mappings for PCI configuration space are used.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieral...@arm.com>
Cc: Bjorn Helgaas <bhelg...@google.com>
Cc: Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com>
Cc: Michal Simek <michal.si...@xilinx.com>
---
 drivers/pci/host/pcie-xilinx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 7f030f5..e96f4a7 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -606,7 +606,7 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port 
*port)
                return err;
        }
 
-       port->reg_base = devm_ioremap_resource(dev, &regs);
+       port->reg_base = devm_ioremap_nopost_resource(dev, &regs);
        if (IS_ERR(port->reg_base))
                return PTR_ERR(port->reg_base);
 
-- 
2.10.0

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