RE: [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI

[Liang, Kan]

> 
> On Mon, 27 Mar 2017, kan.li...@intel.com wrote:
> > +
> > +   if (val)
> > +           msr_set_bit_on_cpus(cpu_possible_mask,
> MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
> > +   else
> > +           msr_clear_bit_on_cpus(cpu_possible_mask,
> MSR_IA32_DEBUGCTLMSR,
> > +DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
> 
> This is still not protected against CPU hotplug. What's so hard about:
> 
>       get_online_cpus();
> 
>       if (val) {
>               msr_set_bit_on_cpus(cpu_online_mask,
> MSR_IA32_DEBUGCTLMSR,
>                                   DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
>       } else {
>               msr_clear_bit_on_cpus(cpu_online_mask,
> MSR_IA32_DEBUGCTLMSR,
> 
> DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
>       }
> 
>       put_online_cpus();
> 
> Aside of that, when this is set to SMI freeze, what causes a CPU which
> comes online after that point to set the bit as well? Nothing AFAICT.
> 
> 

I've patched the intel_pmu_cpu_starting.
I think it guarantees that the new online CPU is set.

@@ -3174,6 +3174,11 @@ static void intel_pmu_cpu_starting(int cpu)
 
        cpuc->lbr_sel = NULL;
 
+       if (x86_pmu.attr_freeze_on_smi)
+               msr_set_bit_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, 
DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
+       else
+               msr_clear_bit_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, 
DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
+
        if (!cpuc->shared_regs)
                return;

Thanks,
Kan