On Wed, Apr 5, 2017 at 2:11 PM, Maxime Ripard <maxime.rip...@free-electrons.com> wrote: > On Wed, Apr 05, 2017 at 11:51:45AM +0800, Chen-Yu Tsai wrote: >> On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng <icen...@aosc.io> wrote: >> > Allwinner A64 SoC features a NMI controller, which is usually connected >> > to the AXP PMIC. >> > >> > Add support for it. >> > >> > Signed-off-by: Icenowy Zheng <icen...@aosc.io> >> >> This might not be the best representation of the R_INTC block. Though >> we'd need to change it for all SoCs if we want to be accurate. For now, > > What do you think would be a good representation?
My gut feeling is that this is the old INTC from sun4/5i. It's supposed to be the interrupt controller for the embedded low power core. I've not done a thorough comparison though. ChenYu
