Documentation bindings for the Low Power General Purpose Register available on i.MX6 SoCs in the Secure Non-Volatile Storage.
Signed-off-by: Oleksij Rempel <[email protected]> Cc: Srinivas Kandagatla <[email protected]> Cc: Maxime Ripard <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] --- Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt new file mode 100644 index 000000000000..5399087a76d1 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt @@ -0,0 +1,15 @@ +Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D +Secure Non-Volatile Storage. + +Required properties: +- compatible: should be one of + "fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S). +- offset: Should contain the offset relative to syscon parent node. +- regmap: Should contain a phandle pointing to syscon. + +Example: + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx6q-snvs-lpgpr"; + regmap = <&snvs>; + offset = <0x68>; + }; -- 2.11.0
