On 04/25/2017 06:29 AM, Andy Shevchenko wrote:
On Mon, Apr 10, 2017 at 1:00 AM, Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppusw...@linux.intel.com> wrote:
According to Broxton APL spec, PMC MIMO resources for Global Control
Registers(GCR) are located at 4K(0x1000) offset from IPC base address.
In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR
region base address from IPC base address and its current value of
0x1008 is incorrect because it points to location for PMC_CFG register
and not the GCR base address itself.
GCR Base = IPC1 Base + 0x1000.
This patch fixes this offset issue.
The whole series has been pushed to testing, thanks.
Thanks Andy.
Signed-off-by: Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppusw...@linux.intel.com>
---
drivers/platform/x86/intel_pmc_ipc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Changes since v6:
* Updated commit message
Changes since v5:
* None
Changes since v4:
* None
Changes since v3:
* Updated the commit history
diff --git a/drivers/platform/x86/intel_pmc_ipc.c
b/drivers/platform/x86/intel_pmc_ipc.c
index 0651d47..0a33592 100644
--- a/drivers/platform/x86/intel_pmc_ipc.c
+++ b/drivers/platform/x86/intel_pmc_ipc.c
@@ -82,7 +82,7 @@
/* exported resources from IFWI */
#define PLAT_RESOURCE_IPC_INDEX 0
#define PLAT_RESOURCE_IPC_SIZE 0x1000
-#define PLAT_RESOURCE_GCR_OFFSET 0x1008
+#define PLAT_RESOURCE_GCR_OFFSET 0x1000
#define PLAT_RESOURCE_GCR_SIZE 0x1000
#define PLAT_RESOURCE_BIOS_DATA_INDEX 1
#define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
--
2.7.4
--
Sathyanarayanan Kuppuswamy
Android kernel developer
