On Thu, May 4, 2017 at 11:00 AM, Benoît Thébaudeau <[email protected]> wrote:
> On 04/05/2017 10:47, Arnd Bergmann wrote:
>> On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau <[email protected]>
>> wrote:
>>> The eSDHC can only DMA from 32-bit-aligned addresses.
>>>
>>> This fixes the following test cases of mmc_test:
>>> 11: Badly aligned write
>>> 12: Badly aligned read
>>> 13: Badly aligned multi-block write
>>> 14: Badly aligned multi-block read
>>>
>>> Signed-off-by: Benoît Thébaudeau <[email protected]>
>>
>> Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR
>> was for devices that cannot address high memory above 0xffffffff, rather than
>> requiring a specific alignment.
>>
>> If this is indeed an address range problem rather than an alignment problem,
>> are you sure it is the SD controller that is wrong here, rather than having a
>> 64-bit DMA capable SDHCI connected to a 32-bit parent bus? In the
>> latter case, the dma-ranges property in the parent bus should limit
>> the addressing, not the device.
>
> No, this is the right description. This quirk really is about alignment, and
> not
> about address range. See:
>
> drivers/mmc/host/sdhci.h:
>>---
> /* Controller can only DMA from 32-bit aligned addresses */
> #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
> <---
>
> drivers/mmc/host/sdhci.c @ sdhci_prepare_data():
>>---
> offset_mask = 0;
> [...]
> if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
> offset_mask = 3;
Ok, thanks for the clarification. I guess I should have checked this myself
first.
Arnd
