Guenter Roeck <li...@roeck-us.net> wrote: > Turns out not here because ____cacheline_aligned_in_smp includes > __page_aligned_data which also declares the section, at least on x86.
If there's any sort of section specification, that should suffice, I think. The problem might come that jiffies and jiffies_64 don't coincide at the same address because FRV is BE not LE. It ought to be possible to make jiffies 64-bit on FRV since it has double-word instructions that can load/store aligned 64-bit values atomically to/from a register pair. That might require some compiler magic, though. I'll have to try and work out if that's possible. David