On Fri, 12 May 2017, kan.li...@intel.com wrote: > From: Kan Liang <kan.li...@intel.com> > > Currently, the SMIs are visible to all performance counters. Because > many users want to measure everything including SMIs. But in some > cases, the SMI cycles should not be count. For example, to calculate > the cost of SMI itself. So a knob is needed. > > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance > counters will be effected. There is no way to do per-counter freeze > on SMI. So it should not use the per-event interface (e.g. ioctl or > event attribute) to set FREEZE_WHILE_SMM bit. > > Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM > bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages > while in SMM. > Value has to be 0 or 1. It will be applied to all processors. > Also serialize the entire setting so we don't get multiple concurrent > threads trying to update to different values. > > Signed-off-by: Kan Liang <kan.li...@intel.com>
Reviewed-by: Thomas Gleixner <t...@linutronix.de>
