On Wed, May 3, 2017 at 7:05 AM, Benoît Thébaudeau <[email protected]> wrote: > On i.MX, SYSCTL.SDCLKFS may always be set to 0 in order to make the SD > clock frequency prescaler divide by 1 in SDR mode, even with the eSDHC. > The previous minimum prescaler value of 2 in SDR mode with the eSDHC was > a code remnant from PowerPC, which actually has this limitation on > earlier revisions. > > In DDR mode, the prescaler can divide by up to 512. > > The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25, > this change makes it possible to get 48 MHz from the USB PLL > (240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL > (240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2). > > Signed-off-by: Benoît Thébaudeau <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
