On Wed, 31 May 2017, Peter Zijlstra wrote: > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014), ... > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), ... > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
Maybe these revisions need to be decreased by one, so that the SGX behavior of messing with the microcode revision is taken into account? When the processor microcode is auto-updated from the (signed) FIT, and SGX's PRMRR feature is supported, the processor will report its microcode revision as one less. Therefore, a microcode update with revision 0xb2 auto-loaded from FIT would be reported by RDMSR(0x8b) as revision 0xb1. I know about this SGX-related behavior from a coreboot commit from ~two years ago (link below). As far as I can tell, the Intel 64/IA32 SDM is *still* missing any mention about this behavior in vol 3A section 9.11 (where it describes microcode updates). https://review.coreboot.org/cgit/coreboot.git/commit/?id=5042aad4ded1651638ae9b60e34114b65e4f211e -- Henrique Holschuh
