On Mon, Jun 05, 2017 at 02:53:47PM -0500, Yazen Ghannam wrote:
> From: Yazen Ghannam <[email protected]>
>
> AMD systems have non-core, shared MCA banks within a Die. These banks are
> controlled by a master CPU per Die. If this CPU is offlined then all the
> shared banks are disabled in addition to the CPU's core banks.
>
> Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
> between SMT thread siblings. If a CPU is offlined then all its sibling's
> MCA banks are also disabled.
>
> Do a vendor check for AMD and return early when offling a CPU.
>
> Signed-off-by: Yazen Ghannam <[email protected]>
> ---
> arch/x86/kernel/cpu/mcheck/mce.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/mcheck/mce.c
> b/arch/x86/kernel/cpu/mcheck/mce.c
> index 5cfbaeb..e317a95 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> @@ -1917,7 +1917,8 @@ static void vendor_disable_error_reporting(void)
> * inhibit reporting for all shared resources on the socket like the
> * last level cache (LLC), the integrated memory controller (iMC), etc.
> */
> - if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
> + boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> return;
>
> mce_disable_error_reporting();
> --
Applied, thanks.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
