On Tue, Jun 06, 2017 at 03:08:50PM +0200, Paolo Bonzini wrote: > > > On 06/06/2017 12:53, Peter Zijlstra wrote: > > On Mon, Jun 05, 2017 at 03:09:50PM -0700, Paul E. McKenney wrote: > >> There would be a slowdown if 1) fast this_cpu_inc is not available and > >> cannot be implemented (this usually means that atomic_inc has implicit > >> memory barriers), > > > > I don't get this. > > > > How is per-cpu crud related to being strongly ordered? > > > > this_cpu_ has 3 forms: > > > > x86: single instruction > > arm64,s390: preempt_disable()+atomic_op > > generic: local_irq_save()+normal_op > > > > Only s390 is TSO, arm64 is very much a weak arch. > > Right, and thus arm64 can implement a fast this_cpu_inc using LL/SC. > s390 cannot because its atomic_inc has implicit memory barriers.
I'm not sure the ordering makes a useful differentiator between a fast and non-fast this_cpu implementation. For TSO archs making their atomic primitives fully ordered isn't _that_ much of a burden over their normal ordering requirements. And LL/SC archs can have very slow (weak) atomics (PPC for example). (Now theoretically a TSO arch could have weak(er) atomics, but I'm not aware of any that do this). I realize we're splitting hairs and slightly off topic :-)
