On Thu, Jun 08, 2017 at 12:39:28PM -0700, Dave Hansen wrote: > > From: Dave Hansen <dave.han...@linux.intel.com> > > Our SMP boot code has a series of assumptions about what NUMA > nodes are that are enforced via topology_sane(). Once upon a > time, we verified that a CPU package only contained a single node > (fixed in cebf15eb0). Today, we verify that SMT siblings and > LLCs do not span nodes. > > The SMT siblings assumption is safe, but the LLC is violated on > current hardware.
What does? That does sound broken. How can a cache domain sanely span memory controllers? This needs far more explanation.
