Hi,
On Fri, 9 Jun 2017 13:58:15 +0300 Leonard Crestez wrote:
> On Thu, 2017-06-08 at 13:45 -0300, Fabio Estevam wrote:
> > On Thu, Jun 8, 2017 at 1:26 PM, Leonard Crestez wrote:
> >
> > >
> > > + tempmon: tempmon {
> > > + compatible = "fsl,imx6ul-tempmon",
> > > "fsl,imx6sx-tempmon";
> > > + interrupts = ;
> > > + fsl,tempmon = <&anatop>;
> > > + fsl,tempmon-data = <&ocotp>;
> > > + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
> > Does the IMX6UL_CLK_PLL3_USB_OTG clock really control tempmon? Please
> > double check.
>
> Yes, as far as I can tell the tempmon block uses the 480 Mhz PLL3 clock
> directly. This is similar to other imx6 SOCs. This PLL is used for
> stuff like USB but not only that. My understanding is the _USB_OTG
> suffix is descriptive, similar to PLL4_AUDIO and PLL6_ENET. Other non-
> usb components use PLL3 (like UART) but through other gates/dividers.
>
> Setting this to IMX6UL_CLK_DUMMY will cause temperature reads to fail.
> Even if PLL3 usually ends up being constantly enabled because of uarts
> this is not true at imx_thermal_probe time (or uarts can be disabled).
>
Since the driver is accessing the OCOTP registers it definitely needs
the IMX6UL_CLK_OCOTP too!
Lothar Waßmann
