On Wed, Jun 14, 2017 at 3:18 PM, Dave Hansen <dave.han...@intel.com> wrote: > On 06/13/2017 09:56 PM, Andy Lutomirski wrote: >> 2. Mms that have been used recently on a given CPU might get to keep >> their TLB entries alive across process switches with this patch >> set. TLB fills are pretty fast on modern CPUs, but they're even >> faster when they don't happen. > > Let's not forget that TLBs are also getting bigger. The bigger TLBs > help ensure that they *can* survive across another process's timeslice. > > Also, the cost to refill the paging structure caches is going up. Just > think of how many cachelines you have to pull in to populate a > ~1500-entry TLB, even if the CPU hid the latency of those loads.
Then throw EPT into the mix for extra fun. I wonder if we should try to allocate page tables from nearby physical addresses if we think we might be running as a guest.
