On Thu, Jun 15, 2017 at 8:40 AM, Liang, Kan <kan.li...@intel.com> wrote:
>
>
>> This patch adds support for SKID_IP to Intel x86 processors in PEBS mode. In
>> that case, the off-by-1 IP from PEBS is returned in the SKID_IP field.
>
> It looks we can only get different skid_ip and ip with :pp event
> (attr.precise = 2).
> With the :p event (attr.precise = 1), the skid_ip and ip are the same. Right?
>
Correct, because skid_ip would be equal to the pebs->ip.
> Thanks,
> Kan
>
>>
>> Signed-off-by: Stephane Eranian <eran...@google.com>
>> ---
>> arch/x86/events/intel/ds.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index
>> c6d23ffe422d..ee17de5d6b8d 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -1169,6 +1169,13 @@ static void setup_pebs_sample_data(struct
>> perf_event *event,
>> x86_pmu.intel_cap.pebs_format >= 1)
>> data->addr = pebs->dla;
>>
>> + /*
>> + * unmodified, skid IP which is guaranteed to be the next
>> + * dyanmic instruction
>> + */
>> + if (sample_type & PERF_SAMPLE_SKID_IP)
>> + data->skid_ip = pebs->ip;
>> +
>> if (x86_pmu.intel_cap.pebs_format >= 2) {
>> /* Only set the TSX weight when no memory weight. */
>> if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
>> --
>> 2.13.1.518.g3df882009-goog
>
