On Mon, Jun 12, 2017 at 5:34 PM, Gregory CLEMENT <[email protected]> wrote:
> From: Hanna Hawa <[email protected]> > > This commit adds a pinctrl driver for the CP110 part of the Marvell > Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all > the MPP pins are available. On the other side, the Armada 8K has two > CP110, and the available MPPs are split between the master CP110 (MPPs 32 > to 62) and the slave CP110 (MPPs 0 to 31). > > The register interface to control the MPPs is however the same as all > other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic. > > Signed-off-by: Hanna Hawa <[email protected]> > Reviewed-by: Shadi Ammouri <[email protected]> > > [updated for mvebu pinctrl and 4.9 changes: > - converted to simple_mmio > - converted to syscon/regmap > - removed unimplemented .remove function > - dropped DTS changes > - defered gpio ranges to DT > - fixed warning > - properly set soc->nmodes > -- rmk] > Signed-off-by: Russell King <[email protected]> > > [ add missing MPP[61:56] function 14 (SDIO) > -- Konstantin Porotchkin] > Signed-off-by: Konstantin Porotchkin <[email protected]> > > [ allow to properly register more then one instance of this driver > -- Grzegorz Jaszczyk] > Signed-off-by: Grzegorz Jaszczyk <[email protected]> > > [ - rebased on 4.12-rc1 > - fixed the 80 character limit for mvebu_mpp_mode array > - aligned the compatible name on the ones already used > - fixed the MPP table for CP110: some MPP are not available on Armada 7K > -- Gregory CLEMENT] > Signed-off-by: Gregory CLEMENT <[email protected]> > > Tested-by: Thomas Petazzoni <[email protected]> Patch applied. Yours, Linus Walleij
