On Monday, July 17, 2017 5:28 AM, Joao Pinto wrote:
>
> Hi,
>
> Às 11:35 AM de 7/13/2017, Jisheng Zhang escreveu:
> > The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> > may also be set. To check whether the ATU is enabled or not, we should
> > test the enable it.
To Jisheng Zhang,
typo s/it/bit
"test the enable it." ---> "test the enable bit."
Please fix this typo, and send it again.
Type is confusing.
Best regards,
Jingoo Han
> >
> > Signed-off-by: Jisheng Zhang <jszh...@marvell.com>
> > ---
> > drivers/pci/dwc/pcie-designware.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> > index 0e03af279259..6bf0b409050a 100644
> > --- a/drivers/pci/dwc/pcie-designware.c
> > +++ b/drivers/pci/dwc/pcie-designware.c
> > @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
> > */
> > for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
> > val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> > - if (val == PCIE_ATU_ENABLE)
> > + if (val & PCIE_ATU_ENABLE)
> > return;
> >
> > usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> >
> Make sense, turn it more accurate. Thanks!
>
> Acked-by: Joao Pinto <jpi...@synopsys.com>
