Refactoring in preparation for subsequent changes. There is no functional change.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com> --- arch/x86/kernel/cpu/amd.c | 79 ++++++++++++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 35 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bb5abe8..74d8d7c 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -297,54 +297,63 @@ static int nearby_node(int apicid) #endif /* - * Fixup core topology information for - * (1) AMD multi-node processors - * Assumption: Number of cores in each internal node is the same. - * (2) AMD processors supporting compute units + * Get topology information via X86_FEATURE_TOPOEXT */ -#ifdef CONFIG_SMP -static void amd_get_topology(struct cpuinfo_x86 *c) +static void __get_topoext(struct cpuinfo_x86 *c) { - u8 node_id; + u32 eax, ebx, ecx, edx; int cpu = smp_processor_id(); - /* get information required for multi-node processors */ - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - u32 eax, ebx, ecx, edx; + cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); - cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); + smp_num_siblings = ((ebx >> 8) & 0xff) + 1; - node_id = ecx & 0xff; - smp_num_siblings = ((ebx >> 8) & 0xff) + 1; + if (c->x86 == 0x15) + c->cu_id = ebx & 0xff; - if (c->x86 == 0x15) - c->cu_id = ebx & 0xff; + if (c->x86 >= 0x17) { + c->cpu_core_id = ebx & 0xff; - if (c->x86 >= 0x17) { - c->cpu_core_id = ebx & 0xff; + if (smp_num_siblings > 1) + c->x86_max_cores /= smp_num_siblings; + } - if (smp_num_siblings > 1) - c->x86_max_cores /= smp_num_siblings; - } + /* + * We may have multiple LLCs if L3 caches exist, so check if we + * have an L3 cache by looking at the L3 cache CPUID leaf. + */ + if (cpuid_edx(0x80000006)) { + if (c->x86 == 0x17) { + /* + * LLC is at the core complex level. + * Core complex id is ApicId[3]. + */ + per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; + } else { + /* LLC is at the node level. */ + u8 node_id = ecx & 0xff; - /* - * We may have multiple LLCs if L3 caches exist, so check if we - * have an L3 cache by looking at the L3 cache CPUID leaf. - */ - if (cpuid_edx(0x80000006)) { - if (c->x86 == 0x17) { - /* - * LLC is at the core complex level. - * Core complex id is ApicId[3]. - */ - per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; - } else { - /* LLC is at the node level. */ - per_cpu(cpu_llc_id, cpu) = node_id; - } + per_cpu(cpu_llc_id, cpu) = node_id; } + } +} + +/* + * Fixup core topology information for + * (1) AMD multi-node processors + * Assumption: Number of cores in each internal node is the same. + * (2) AMD processors supporting compute units + */ +#ifdef CONFIG_SMP +static void amd_get_topology(struct cpuinfo_x86 *c) +{ + /* get information required for multi-node processors */ + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { + __get_topoext(c); } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { + u8 node_id; u64 value; + int cpu = smp_processor_id(); rdmsrl(MSR_FAM10H_NODE_ID, value); node_id = value & 7; -- 2.7.4