On Thu, Aug 03, 2017 at 10:05:16PM +0800, Boqun Feng wrote:
> Hi Will,
>
> On Wed, Aug 02, 2017 at 10:45:32AM +0100, Will Deacon wrote:
> [...]
> >
> > It's worth noting that we don't have the problem with any value-returning
> > atomics, so all flavours of xchg in this test would be forbidden on arm64
> > too.
> >
> > > C C-WillDeacon-MP+o-r+ai-rmb-o.litmus
> > >
> > > (*
> > > * Expected result: Never.
> > > *
> > > * Desired litmus test, with atomic_inc() emulated by xchg_relaxed():
> > > *
> > > * WRITE_ONCE(x, 1); atomic_inc(&y);
> > > * r0 = xchg_release(&y, 5); smp_rmb();
> > > * r1 = READ_ONCE(x);
> > > *
> > > *
> > > * WARN_ON(r0 == 0 && r1 == 0);
> > > *)
> > >
> > > {
> > > }
> > >
> > > P0(int *x, int *y)
> > > {
> > > WRITE_ONCE(*x, 1);
> > > r0 = xchg_release(y, 5);
> > > }
> > >
> > > P1(int *x, int *y)
> > > {
> > > r2 = xchg_relaxed(y, 1);
> > > smp_rmb();
> > > r1 = READ_ONCE(*x);
> > > }
> > >
> > > exists
> > > (0:r0=0 /\ 1:r1=0)
> > >
>
> How about a litmus test like this?
>
> C C-AMO-global-transitivity.litmus
>
> {
> }
>
> P0(int *x, int *y)
> {
> WRITE_ONCE(*x, 1);
> r0 = xchg_release(y, 5);
> }
>
> P1(int *y, int *z)
> {
> atomic_inc(y);
> smp_mb();
I am going to guess that the smp_mb() enforces the needed ordering,
but Will will let me know. ;-)
Thanx, Paul
> r1 = READ_ONCE(*z);
> }
>
> P2(int *x, int *z)
> {
> WRITE_ONCE(*z, 1);
> smp_mb();
> r2 = READ_ONCE(*x);
> }
>
> exists
> (0:r0=0 /\ 1:r1=0 /\ 2:r2=0 )
>
> Should we forbid the outcome in the exists-clause? I ask because I want
> to know whether we can just treat atomic_inc() as a store, because if I
> replace atomic_inc() with a WRITE(*y, 6), IIUC, the current model says
> this could happen.
>
> Thoughts?
>
> Regards,
> Boqun
