On 08/10, Quentin Schulz wrote: > This new clock driver set allows to have a fractional divided clock that > would generate a precise clock particularly suitable for audio > applications. > > The main audio pll clock has two children clocks: one that is connected > to the PMC, the other that can directly drive a pad. As these two routes > have different enable bits and different dividers and divider formulas, > they are handled by two different drivers. Each of them could modify the > rate of the main audio pll parent. > > The main audio pll clock can output 620MHz to 700MHz. > > Signed-off-by: Nicolas Ferre <nicolas.fe...@atmel.com> > Signed-off-by: Quentin Schulz <quentin.sch...@free-electrons.com> > Acked-by: Boris Brezillon <boris.brezil...@free-electrons.com> > ---
Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
