On 2017年08月29日 07:12, Vikram Mulukutla wrote:
Well here's something interesting. I tried a different platform and
found that
the workaround doesn't help much at all, similar to Qiao's observation
on his b.L
chipset. Something to do with the WFE implementation or event-stream?
Hi Vikram,
I did some experiments, to tune the ddr controller(and ddr ram) freq,
and cci freq. And the result is as below:
cpu2: a53, 832MHz, cpu7: a73, 1.75Hz
cci: 832M
dclk: DDR controller clock.(data rate = 4 * dclk)
With cpu_relax bodging patch:
==============================================================
dclk | cpu2 time | cpu2 counter | cpu7 time | cpu7 counter |
=======|===========|==============|===========|==============|
78M | 8906| 55438| 13| 4015789|
156M | 5964| 75109| 4| 8229050|
500M | 102| 5984783| 1| 6400885|
600M | 16| 6233601| 1| 6504718|
==============================================================
I suspect that the global exclusive monitor in ddr controller may play
an important part. With ddr frequency is higher enough, it seems to
handle the exclusive requests efficiently and fairly.
If reducing cci freq to a lower value, the result of little core drops a
lot again.
cpu2: a53, 832MHz, cpu7: a73, 1.75Hz
cci: 416M
dclk: DDR controller clock.(data rate = 4 * dclk)
With cpu_relax bodging patch:
==============================================================
dclk | cpu2 time | cpu2 counter | cpu7 time | cpu7 counter |
=======|===========|==============|===========|==============|
78M | 8837| 10596| 11| 3873635|
156M | 17597| 10211| 4| 6513493|
500M | 10888| 13214| 2| 8916396|
600M | 8934| 15842| 2| 9394124|
==============================================================
I guess the result on your different platform might be related with DDR
frequency too.
Best Regards
Qiao
