On 2017.09.09 at 11:26 -0700, Linus Torvalds wrote: > On Sat, Sep 9, 2017 at 11:14 AM, Markus Trippelsdorf > <mar...@trippelsdorf.de> wrote: > > > > I think the issue gets fixed by: > > > > # wrmsr -a 0xc0010015 0x1000018 > > > > Setting bit 3 of the Hardware Configuration Register to 1. > > > > Quote from the docs: > > »TlbCacheDis: cacheable memory disable. Read-write. 0=Enables performance > > optimization that > > assumes PML4, PDP, PDE, and PTE entries are in cacheable WB-DRAM > > Uhhuh. > > The page directories should *definitely* always be in cacheable > memory, so it should be ok for that bit to be 0, and it's possible > that setting it to 1 will seriously screw up performance.
Well, I don't see any dramatic performance decrease on my box. For instance compile times are roughly the same (a bit quicker in fact). And in day to day usage I notice absolutely no difference. -- Markus
