Re: [PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33

[icenowy]

在 2017-09-14 23:51，Levin, Alexander (Sasha Levin) 写道：

From: Icenowy Zheng <icen...@aosc.xyz>

[ Upstream commit bb021cda2ccf45ee9470bf0f8c55323ad1c761ae ]

As DVFS for A33 doesn't exist in 4.9, this patch doesn't affect 4.9
at all.

The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to
be changeable by changing the rate of PLL_CPUX.

Add CLK_SET_RATE_PARENT flag to this clock.

Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Signed-off-by: Sasha Levin <alexander.le...@verizon.com>
---
 drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index 9bd1f78a0547..d54e5db3959a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c

@@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",

 static const char * const cpux_parents[] = { "osc32k", "osc24M",
                                             "pll-cpux" , "pll-cpux" };
 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
-                    0x050, 16, 2, CLK_IS_CRITICAL);
+                    0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);

 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);