On Mon, Sep 18, 2017 at 03:03:30PM +0800, 陈华才 wrote: > I don't think dma_get_cache_alignment is the "absolute minimum alignment" in > all cases. At least on MIPS/Loongson, if we use I/O coherent mode (Cached DMA > mode), align block queue to 4Bytes is enough. If we align block queue to > dma_get_cache_alignment in I/O coherent mode, there are peformance lost > because we cannot use zero-copy in most cases (user buffers are usually not > aligned).
If you systems is I/O coherent it should report 1 ARCH_DMA_MINALIGN / dma_get_cache_alignment(). Note that many drivers only support 512 byte aligned mappings for block I/O and they've done pretty fine so far.
