On Sat, Apr 28, 2007 at 02:08:58PM -0400, Jeff Garzik wrote:
> Andi Kleen wrote:
> > From: Simon Arlott <[EMAIL PROTECTED]>
> >
> > The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has
> > a cache line length of 64 according to
> > http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets
> > gcc to -march=686 and select s the correct cache shift.
> >
> > Signed-off-by: Simon Arlott <[EMAIL PROTECTED]>
> > Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
> > Cc: Andi Kleen <[EMAIL PROTECTED]>
> > Cc: Dave Jones <[EMAIL PROTECTED]>
> > Cc: Alan Cox <[EMAIL PROTECTED]>
> > Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
>
> Has it been verified in the field that this CPU supports CMOV?
Yes. All their CPUs for some time now have done so.
Dave
--
http://www.codemonkey.org.uk
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