Add device-tree binding documentation for the Qualcom APCS clock
controller. This clock controller is a mux and half-integer divider
and provides the clock for the application CPU.

Signed-off-by: Georgi Djakov <georgi.dja...@linaro.org>
---
 .../devicetree/bindings/clock/qcom,apcs.txt        | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,apcs.txt

diff --git a/Documentation/devicetree/bindings/clock/qcom,apcs.txt 
b/Documentation/devicetree/bindings/clock/qcom,apcs.txt
new file mode 100644
index 000000000000..8083bcc33ebe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,apcs.txt
@@ -0,0 +1,27 @@
+Qualcomm APCS Clock Controller Binding
+--------------------------------------
+The APCS hardware block provides a combined mux and half-integer divider
+functionality. It is used for a main CPU clock mux on MSM8916 platforms.
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+               "qcom,msm8916-apcs-clk"
+
+- clocks : shall be the phandle to the main input CPU PLL clock
+
+- #clock-cells : must be set to <0>
+
+Example:
+
+       apcs: mailbox@b011000 {
+               compatible = "qcom,msm8916-apcs-kpss-global";
+               reg = <0xb011000 0x1000>;
+               #mbox-cells = <1>;
+
+               apcs_clk: apcs_clk {
+                       compatible = "qcom,msm8916-apcs-clk";
+                       clocks = <&a53pll>;
+                       #clock-cells = <0>;
+               };
+       };

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