[PATCH v2 6/8] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock

[Nickey Yang]

Mipi-dphy's ref_clk connect to clk_dphy_pll inside rk3399.
clk_24m -> Gate11[14] -> clk_mipidphy_ref -> Gate21[0] -> clk_dphy_pll
So correct it.

Signed-off-by: Nickey Yang <nickey.y...@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d79e9b3..6aa43fd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1629,7 +1629,7 @@
                compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
                reg = <0x0 0xff960000 0x0 0x8000>;
                interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
-               clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+               clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
                         <&cru SCLK_DPHY_TX0_CFG>;
                clock-names = "ref", "pclk", "phy_cfg";
                power-domains = <&power RK3399_PD_VIO>;
-- 
1.9.1