On Thu, Sep 28, 2017 at 01:03:39PM -0500, mike.tra...@hpe.com wrote: > > The UV BIOS goes to considerable effort to get the TSC synchronization > accurate across the entire system. Included in that are multiple chassis > that can have 32+ sockets. The architecture does support an external > high resolution clock to aid in maintaining this synchronization. > > The resulting TSC accuracy set by the UV system BIOS is much better > than the generic kernel TSC ADJUST functions. This is important for > applications that read the TSC values directly for accessing data bases. > > * These patches disable an assumption made by the kernel tsc sync > functions that Socket 0 in the system should have a TSC ADJUST > value of zero. This is not correct when the chassis are reset > asynchronously to each other so which TSC's should be zero is > not predictable. > > * When the system BIOS determines that the TSC is not stable, it then > sets a flag so the UV kernel setup can set the "tsc is unstable" > flag. A patch now prevents the kernel from attempting to fix the > TSC causing a slew of warning messages. > > * It also eliminates another avalanche of warning messages from older > BIOS that did not have the TSC ADJUST MSR (ex. >3000 msgs in a 32 > socket Skylake system). It now notes this with a single warning > message and then moves on with fixing them.
So I would still like to get clarification on how ART works (or likely doesn't) on your systems. I think for now its fairly prudent to kill detect_art() on UV. Also, while indeed not strictly required, that TSC_ADJUST==0 test on bootcpu is nice for consumer systems, BIOS did something 'weird' if that is not true. Is something like is_uv_system() available early enough? Other than that, the patches look good to me.
