2017-09-28 18:04-0700, Wanpeng Li:
> From: Wanpeng Li <wanpeng...@hotmail.com>
> 
> SDM 10.5.4.1 TSC-Deadline Mode mentioned that "Transitioning between 
> TSC-Deadline
> mode and other timer modes also disarms the timer". So the APIC Timer Initial 
> Count
> Register for one-shot/periodic mode should be reset. This patch do it.

At the beginning of the secion is also:

  A write to the LVT Timer Register that changes the timer mode disarms
  the local APIC timer. The supported timer modes are given in Table
  10-2. The three modes of the local APIC timer are mutually exclusive.

So we should also disarm when switching between one-shot and periodic.

apic_update_lvtt() already has logic to determine whether the timer mode
has changed and is the perfect place to clear APIC_TMICT.

Thanks.

> Cc: Paolo Bonzini <pbonz...@redhat.com>
> Cc: Radim Krčmář <rkrc...@redhat.com>
> Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com>
> ---
>  arch/x86/include/asm/apicdef.h | 1 +
>  arch/x86/kvm/lapic.c           | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
> index c46bb99..d8ef1b4 100644
> --- a/arch/x86/include/asm/apicdef.h
> +++ b/arch/x86/include/asm/apicdef.h
> @@ -100,6 +100,7 @@
>  #define              APIC_TIMER_BASE_CLKIN           0x0
>  #define              APIC_TIMER_BASE_TMBASE          0x1
>  #define              APIC_TIMER_BASE_DIV             0x2
> +#define              APIC_LVT_TIMER_MASK             (3 << 17)
>  #define              APIC_LVT_TIMER_ONESHOT          (0 << 17)
>  #define              APIC_LVT_TIMER_PERIODIC         (1 << 17)
>  #define              APIC_LVT_TIMER_TSCDEADLINE      (2 << 17)
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 69c5612..a739cbb 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -1722,6 +1722,9 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 
> reg, u32 val)
>               break;
>  
>       case APIC_LVTT:
> +             if (apic_lvtt_tscdeadline(apic) != ((val &
> +                     APIC_LVT_TIMER_MASK) == APIC_LVT_TIMER_TSCDEADLINE))
> +                     kvm_lapic_set_reg(apic, APIC_TMICT, 0);
>               if (!kvm_apic_sw_enabled(apic))
>                       val |= APIC_LVT_MASKED;
>               val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
> -- 
> 2.7.4
> 

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