On Tue, Sep 26, 2017 at 02:22:04AM +0300, Dmitry Osipenko wrote:
> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
> on Tegra20/30 SoC's.
>
> Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
> ---
> .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23
> ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
> b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
> new file mode 100644
> index 000000000000..2af9aa76ae11
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
> @@ -0,0 +1,23 @@
> +* NVIDIA Tegra AHB DMA controller
> +
> +Required properties:
> +- compatible: Must be "nvidia,tegra20-ahbdma"
> +- reg: Should contain registers base address and length.
> +- interrupts: Should contain one entry, DMA controller interrupt.
> +- clocks: Should contain one entry, DMA controller clock.
> +- resets : Should contain one entry, DMA controller reset.
> +- #dma-cells: Should be <1>. The cell represents DMA request select
> value
> + for the peripheral. For more details consult the Tegra TRM's
> + documentation, in particular AHB DMA channel control register
> + REQ_SEL field.
> +
> +Example:
> +
> +ahbdma: ahbdma@60008000 {
Use standard node names. dma-controller in this case.
> + compatible = "nvidia,tegra20-ahbdma";
> + reg = <0x60008000 0x2000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA20_CLK_AHBDMA>;
> + resets = <&tegra_car 33>;
> + #dma-cells = <1>;
> +};
> --
> 2.14.1
>
