2017-10-06 21:59+0800, Wanpeng Li:
> 2017-10-06 21:14 GMT+08:00 Radim Krčmář <rkrc...@redhat.com>:
> > 2017-10-05 18:54-0700, Wanpeng Li:
> >> From: Wanpeng Li <wanpeng...@hotmail.com>
> >>
> >> The description in the Intel SDM of how the divide configuration
> >> register is used: "The APIC timer frequency will be the processor's bus
> >> clock or core crystal clock frequency divided by the value specified in
> >> the divide configuration register."
> >>
> >> Observation of baremetal shown that when the TDCR is change, the TMCCT
> >> does not change or make a big jump in value, but the rate at which it
> >> count down change.
> >>
> >> The patch update the emulation to APIC timer to so that a change to the
> >> divide configuration would be reflected in the value of the counter and
> >> when the next interrupt is triggered.
> >>
> >> Cc: Paolo Bonzini <pbonz...@redhat.com>
> >> Cc: Radim Krčmář <rkrc...@redhat.com>
> >> Signed-off-by: Wanpeng Li <wanpeng...@hotmail.com>
> >> ---
> >> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> >> @@ -1458,6 +1458,36 @@ static void start_sw_period(struct kvm_lapic *apic)
> >> +static bool update_target_expiration(struct kvm_lapic *apic, uint32_t
> >> old_divisor)
> >> +{
> >> + ktime_t now, remaining;
> >> + u64 tscl = rdtsc(), delta;
> >> +
> >> + now = ktime_get();
> >> + remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
> >> + if (ktime_to_ns(remaining) < 0)
> >> + remaining = 0;
> >> + delta = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
> >
> > Hm, can this happen?
>
> Yeah, when the hrtimer has already expired. I can catch it during testing.
I thought that "if (ktime_to_ns(remaining) < 0)" is there to catch that,
isn't that a bug elsewhere?
