Christophe Leroy <christophe.le...@c-s.fr> writes: > IPIC Status is provided by register IPIC_SERSR and not by IPIC_SERMR > which is the mask register.
This seems like it would be a bad bug. But I guess it hasn't mattered for some reason? cheers > diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c > index 16f1edd78c40..535cf1f6941c 100644 > --- a/arch/powerpc/sysdev/ipic.c > +++ b/arch/powerpc/sysdev/ipic.c > @@ -846,12 +846,12 @@ void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq) > > u32 ipic_get_mcp_status(void) > { > - return ipic_read(primary_ipic->regs, IPIC_SERMR); > + return ipic_read(primary_ipic->regs, IPIC_SERSR); > } > > void ipic_clear_mcp_status(u32 mask) > { > - ipic_write(primary_ipic->regs, IPIC_SERMR, mask); > + ipic_write(primary_ipic->regs, IPIC_SERSR, mask); > } > > /* Return an interrupt vector or 0 if no interrupt is pending. */ > -- > 2.13.3