Em Wed, Oct 18, 2017 at 06:05:07AM -0700, kan.li...@intel.com escreveu:
> From: Kan Liang <kan.li...@intel.com>
>
> Add a Intel event file for perf.
Andi, can I have your Acked-by or reviewed-by?
- Arnaldo
> Signed-off-by: Kan Liang <kan.li...@intel.com>
> ---
> .../pmu-events/arch/x86/goldmontplus/cache.json | 1453
> ++++++++++++++++++++
> .../pmu-events/arch/x86/goldmontplus/frontend.json | 62 +
> .../pmu-events/arch/x86/goldmontplus/memory.json | 38 +
> .../pmu-events/arch/x86/goldmontplus/other.json | 98 ++
> .../pmu-events/arch/x86/goldmontplus/pipeline.json | 544 ++++++++
> .../arch/x86/goldmontplus/virtual-memory.json | 218 +++
> tools/perf/pmu-events/arch/x86/mapfile.csv | 1 +
> 7 files changed, 2414 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
> create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
> create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
> create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/other.json
> create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
> create mode 100644
> tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
>
> diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
> b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
> new file mode 100644
> index 0000000..b4791b4
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
> @@ -0,0 +1,1453 @@
> +[
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts memory requests originating from the
> core that miss in the L2 cache.",
> + "EventCode": "0x2E",
> + "Counter": "0,1,2,3",
> + "UMask": "0x41",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "LONGEST_LAT_CACHE.MISS",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "L2 cache request misses"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts memory requests originating from the
> core that reference a cache line in the L2 cache.",
> + "EventCode": "0x2E",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4f",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "LONGEST_LAT_CACHE.REFERENCE",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "L2 cache requests"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of demand and prefetch
> transactions that the L2 XQ rejects due to a full or near full condition
> which likely indicates back pressure from the intra-die interconnect (IDI)
> fabric. The XQ may reject transactions from the L2Q (non-cacheable requests),
> L2 misses and L2 write-back victims.",
> + "EventCode": "0x30",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "L2_REJECT_XQ.ALL",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Requests rejected by the XQ"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of demand and L1 prefetcher
> requests rejected by the L2Q due to a full or nearly full condition which
> likely indicates back pressure from L2Q. It also counts requests that would
> have gone directly to the XQ, but are rejected due to a full or nearly full
> condition, indicating back pressure from the IDI link. The L2Q may also
> reject transactions from a core to insure fairness between cores, or to delay
> a core's dirty eviction when the address conflicts with incoming external
> snoops.",
> + "EventCode": "0x31",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "CORE_REJECT_L2Q.ALL",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Requests rejected by the L2Q"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts when a modified (dirty) cache line is
> evicted from the data L1 cache and needs to be written back to memory. No
> count will occur if the evicted line is clean, and hence does not require a
> writeback.",
> + "EventCode": "0x51",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DL1.REPLACEMENT",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "L1 Cache evictions for dirty data"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts cycles that fetch is stalled due to an
> outstanding ICache miss. That is, the decoder queue is able to accept bytes,
> but the fetch unit is unable to provide bytes due to an ICache miss. Note:
> this event is not the same as the total number of cycles spent retrieving
> instruction cache lines from the memory hierarchy.",
> + "EventCode": "0x86",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Cycles code-fetch stalled due to an outstanding
> ICache miss."
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "EventCode": "0xB7",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts locked memory uops retired. This
> includes regular locks and bus locks. (To specifically count bus locks only,
> see the Offcore response event.) A locked access is one with a lock prefix,
> or an exchange to memory. See the SDM for a complete description of which
> memory load accesses are locks.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x21",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Locked load uops retired (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts load uops retired where the data
> requested spans a 64 byte cache line boundary.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x41",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops retired that split a cache-line
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts store uops retired where the data
> requested spans a 64 byte cache line boundary.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x42",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Stores uops retired that split a cache-line
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts memory uops retired where the data
> requested spans a 64 byte cache line boundary.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x43",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.SPLIT",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Memory uops retired that split a cache-line
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts the number of load uops retired.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x81",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops retired (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts the number of store uops retired.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x82",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Store uops retired (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts the number of memory uops retired that
> is either a loads or a store or both.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x83",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.ALL",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Memory uops retired (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts load uops retired that hit the L1 data
> cache.",
> + "EventCode": "0xD1",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops retired that hit L1 data cache
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts load uops retired that hit in the L2
> cache.",
> + "EventCode": "0xD1",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops retired that hit L2 (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts load uops retired that miss the L1 data
> cache.",
> + "EventCode": "0xD1",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops retired that missed L1 data cache
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts load uops retired that miss in the L2
> cache.",
> + "EventCode": "0xD1",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops retired that missed L2 (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts load uops retired where the cache line
> containing the data was in the modified state of another core or modules
> cache (HITM). More specifically, this means that when the load address was
> checked by other caching agents (typically another processor) in the system,
> one of those caching agents indicated that they had a dirty copy of the data.
> Loads that obtain a HITM response incur greater latency than most is typical
> for a load. In addition, since HITM indicates that some other processor had
> this data in its cache, it implies that the data was shared between
> processors, or potentially was a lock or semaphore value. This event is
> useful for locating sharing, false sharing, and contended locks.",
> + "EventCode": "0xD1",
> + "Counter": "0,1,2,3",
> + "UMask": "0x20",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Memory uop retired where cross core or cross
> module HITM occurred (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts memory load uops retired where the data
> is retrieved from the WCB (or fill buffer), indicating that the load found
> its data while that data was in the process of being brought into the L1
> cache. Typically a load will receive this indication when some other load or
> prefetch missed the L1 cache and was in the process of retrieving the cache
> line containing the data, but that process had not yet finished (and written
> the data back to the cache). For example, consider load X and Y, both
> referencing the same cache line that is not in the L1 cache. If load X
> misses cache first, it obtains and WCB (or fill buffer) and begins the
> process of requesting the data. When load Y requests the data, it will
> either hit the WCB, or the L1 cache, depending on exactly what time the
> request to Y occurs.",
> + "EventCode": "0xD1",
> + "Counter": "0,1,2,3",
> + "UMask": "0x40",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Loads retired that hit WCB (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts memory load uops retired where the data
> is retrieved from DRAM. Event is counted at retirement, so the speculative
> loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or
> miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.",
> + "EventCode": "0xD1",
> + "Counter": "0,1,2,3",
> + "UMask": "0x80",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Loads retired that came from DRAM (Precise
> event capable)"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand cacheable data reads of full
> cache lines have any transaction responses from the uncore subsystem.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010001",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand cacheable data reads of full
> cache lines have any transaction responses from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand cacheable data reads of full
> cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040001",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand cacheable data reads of full
> cache lines hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand cacheable data reads of full
> cache lines true miss for the L2 cache with a snoop miss in the other
> processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000001",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand cacheable data reads of full
> cache lines true miss for the L2 cache with a snoop miss in the other
> processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand cacheable data reads of full
> cache lines miss the L2 cache with a snoop hit in the other processor module,
> data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000001",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand cacheable data reads of full
> cache lines miss the L2 cache with a snoop hit in the other processor module,
> data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand cacheable data reads of full
> cache lines outstanding, per cycle, from the time of the L2 miss to when any
> response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type
> and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000001",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand cacheable data reads of full
> cache lines outstanding, per cycle, from the time of the L2 miss to when any
> response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line have any transaction
> responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010002",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line have any transaction
> responses from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line hit the L2 cache.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040002",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line true miss for the L2
> cache with a snoop miss in the other processor module. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000002",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line true miss for the L2
> cache with a snoop miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line miss the L2 cache with
> a snoop hit in the other processor module, data forwarding is required.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000002",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line miss the L2 cache with
> a snoop hit in the other processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line outstanding, per cycle,
> from the time of the L2 miss to when any response is received. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000002",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand reads for ownership (RFO)
> requests generated by a write to full data cache line outstanding, per cycle,
> from the time of the L2 miss to when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache have any transaction
> responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010004",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache have any transaction
> responses from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache hit the L2 cache. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040004",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache true miss for the L2 cache
> with a snoop miss in the other processor module. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000004",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache true miss for the L2 cache
> with a snoop miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache miss the L2 cache with a
> snoop hit in the other processor module, data forwarding is required.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000004",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache miss the L2 cache with a
> snoop hit in the other processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache outstanding, per cycle,
> from the time of the L2 miss to when any response is received. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000004",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts demand instruction cacheline and I-side
> prefetch requests that miss the instruction cache outstanding, per cycle,
> from the time of the L2 miss to when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions have any transaction responses from the
> uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010008",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions have any transaction responses from the
> uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions hit the L2 cache. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040008",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop
> miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000008",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop
> miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the
> other processor module, data forwarding is required. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000008",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the
> other processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions outstanding, per cycle, from the time of
> the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000008",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts the number of writeback transactions
> caused by L1 or L2 cache evictions outstanding, per cycle, from the time of
> the L2 miss to when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher have any transaction responses from the uncore
> subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher have any transaction responses from the uncore
> subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in
> the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in
> the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other
> processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other
> processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2
> miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cacheline reads generated by
> hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2
> miss to when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher have any transaction responses from the uncore
> subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010020",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher have any transaction responses from the uncore
> subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040020",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher true miss for the L2 cache with a snoop miss in
> the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000020",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher true miss for the L2 cache with a snoop miss in
> the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher miss the L2 cache with a snoop hit in the other
> processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000020",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher miss the L2 cache with a snoop hit in the other
> processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher outstanding, per cycle, from the time of the L2
> miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000020",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> generated by L2 prefetcher outstanding, per cycle, from the time of the L2
> miss to when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts bus lock and split lock requests have
> any transaction responses from the uncore subsystem. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010400",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts bus lock and split lock requests have
> any transaction responses from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts bus lock and split lock requests hit
> the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040400",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts bus lock and split lock requests hit the
> L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts bus lock and split lock requests true
> miss for the L2 cache with a snoop miss in the other processor module.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000400",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts bus lock and split lock requests true
> miss for the L2 cache with a snoop miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts bus lock and split lock requests miss
> the L2 cache with a snoop hit in the other processor module, data forwarding
> is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000400",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts bus lock and split lock requests miss
> the L2 cache with a snoop hit in the other processor module, data forwarding
> is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts bus lock and split lock requests
> outstanding, per cycle, from the time of the L2 miss to when any response is
> received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000400",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts bus lock and split lock requests
> outstanding, per cycle, from the time of the L2 miss to when any response is
> received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes have any transaction responses from the uncore subsystem.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes have any transaction responses from the uncore
> subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes true miss for the L2 cache with a snoop miss in the other
> processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes true miss for the L2 cache with a snoop miss in the other
> processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes miss the L2 cache with a snoop hit in the other processor
> module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes miss the L2 cache with a snoop hit in the other processor
> module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes outstanding, per cycle, from the time of the L2 miss to
> when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts full cache line data writes to
> uncacheable write combining (USWC) memory region and full cache-line
> non-temporal writes outstanding, per cycle, from the time of the L2 miss to
> when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache lines requests by software
> prefetch instructions have any transaction responses from the uncore
> subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000011000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache lines requests by software
> prefetch instructions have any transaction responses from the uncore
> subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache lines requests by software
> prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000041000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache lines requests by software
> prefetch instructions hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache lines requests by software
> prefetch instructions true miss for the L2 cache with a snoop miss in the
> other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request
> type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200001000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache lines requests by software
> prefetch instructions true miss for the L2 cache with a snoop miss in the
> other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache lines requests by software
> prefetch instructions miss the L2 cache with a snoop hit in the other
> processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000001000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache lines requests by software
> prefetch instructions miss the L2 cache with a snoop hit in the other
> processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache lines requests by software
> prefetch instructions outstanding, per cycle, from the time of the L2 miss to
> when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000001000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache lines requests by software
> prefetch instructions outstanding, per cycle, from the time of the L2 miss to
> when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher have any transaction responses from the
> uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000012000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher have any transaction responses from the
> uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher hit the L2 cache. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000042000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher true miss for the L2 cache with a snoop
> miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200002000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher true miss for the L2 cache with a snoop
> miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the
> other processor module, data forwarding is required. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000002000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the
> other processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher outstanding, per cycle, from the time of
> the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000002000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data cache line reads generated by
> hardware L1 data cache prefetcher outstanding, per cycle, from the time of
> the L2 miss to when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region have any transaction responses from the
> uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000014800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region have any transaction responses from the
> uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region hit the L2 cache. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000044800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region true miss for the L2 cache with a snoop miss
> in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200004800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region true miss for the L2 cache with a snoop miss
> in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region miss the L2 cache with a snoop hit in the
> other processor module, data forwarding is required. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000004800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region miss the L2 cache with a snoop hit in the
> other processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region outstanding, per cycle, from the time of the
> L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000004800",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts any data writes to uncacheable write
> combining (USWC) memory region outstanding, per cycle, from the time of the
> L2 miss to when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the uncore subsystem have
> any transaction responses from the uncore subsystem. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000018000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts requests to the uncore subsystem have
> any transaction responses from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the uncore subsystem hit
> the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000048000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts requests to the uncore subsystem hit the
> L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the uncore subsystem true
> miss for the L2 cache with a snoop miss in the other processor module.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200008000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts requests to the uncore subsystem true
> miss for the L2 cache with a snoop miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the uncore subsystem miss
> the L2 cache with a snoop hit in the other processor module, data forwarding
> is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000008000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts requests to the uncore subsystem miss
> the L2 cache with a snoop hit in the other processor module, data forwarding
> is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the uncore subsystem
> outstanding, per cycle, from the time of the L2 miss to when any response is
> received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000008000",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts requests to the uncore subsystem
> outstanding, per cycle, from the time of the L2 miss to when any response is
> received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads generated by L1 or L2
> prefetchers have any transaction responses from the uncore subsystem.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000013010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads generated by L1 or L2
> prefetchers have any transaction responses from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads generated by L1 or L2
> prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000043010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads generated by L1 or L2
> prefetchers hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads generated by L1 or L2
> prefetchers true miss for the L2 cache with a snoop miss in the other
> processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200003010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads generated by L1 or L2
> prefetchers true miss for the L2 cache with a snoop miss in the other
> processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads generated by L1 or L2
> prefetchers miss the L2 cache with a snoop hit in the other processor module,
> data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000003010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads generated by L1 or L2
> prefetchers miss the L2 cache with a snoop hit in the other processor module,
> data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads generated by L1 or L2
> prefetchers outstanding, per cycle, from the time of the L2 miss to when any
> response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type
> and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000003010",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads generated by L1 or L2
> prefetchers outstanding, per cycle, from the time of the L2 miss to when any
> response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads (demand & prefetch) have any
> transaction responses from the uncore subsystem. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000013091",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads (demand & prefetch) have any
> transaction responses from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads (demand & prefetch) hit the
> L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000043091",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads (demand & prefetch) hit the
> L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads (demand & prefetch) true
> miss for the L2 cache with a snoop miss in the other processor module.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200003091",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads (demand & prefetch) true miss
> for the L2 cache with a snoop miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads (demand & prefetch) miss the
> L2 cache with a snoop hit in the other processor module, data forwarding is
> required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000003091",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads (demand & prefetch) miss the
> L2 cache with a snoop hit in the other processor module, data forwarding is
> required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data reads (demand & prefetch)
> outstanding, per cycle, from the time of the L2 miss to when any response is
> received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000003091",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data reads (demand & prefetch)
> outstanding, per cycle, from the time of the L2 miss to when any response is
> received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) have any transaction responses from the uncore subsystem.
> Requires MSR_OFFCORE_RESP[0,1] to specify request type and response.
> (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000010022",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) have any transaction responses from the uncore
> subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0000040022",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) true miss for the L2 cache with a snoop miss in the other
> processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and
> response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x0200000022",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) true miss for the L2 cache with a snoop miss in the other
> processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) miss the L2 cache with a snoop hit in the other processor
> module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to
> specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x1000000022",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) miss the L2 cache with a snoop hit in the other processor
> module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to
> when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify
> request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x4000000022",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts reads for ownership (RFO) requests
> (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to
> when any response is received.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) have any transaction responses
> from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request
> type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x00000132b7",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) have any transaction responses
> from the uncore subsystem.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x00000432b7",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) hit the L2 cache.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with
> a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1]
> to specify request type and response. (duplicated for both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x02000032b7",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName":
> "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with
> a snoop miss in the other processor module. ",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop
> hit in the other processor module, data forwarding is required. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x10000032b7",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6, 0x1a7",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop
> hit in the other processor module, data forwarding is required.",
> + "Offcore": "1"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the
> time of the L2 miss to when any response is received. Requires
> MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for
> both MSRs)",
> + "EventCode": "0xB7",
> + "MSRValue": "0x40000032b7",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING",
> + "PDIR_COUNTER": "na",
> + "MSRIndex": "0x1a6",
> + "SampleAfterValue": "100007",
> + "BriefDescription": "Counts data read, code read, and read for
> ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the
> time of the L2 miss to when any response is received.",
> + "Offcore": "1"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
> b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
> new file mode 100644
> index 0000000..a787896
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json
> @@ -0,0 +1,62 @@
> +[
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the Instruction Cache
> (ICache) for one or more bytes in an ICache Line and that cache line is in
> the ICache (hit). The event strives to count on a cache line basis, so that
> multiple accesses which hit in a single cache line count as one ICACHE.HIT.
> Specifically, the event counts when straight line code crosses the cache line
> boundary, or when a branch target is to a new line, and that cache line is in
> the ICache. This event counts differently than Intel processors based on
> Silvermont microarchitecture.",
> + "EventCode": "0x80",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ICACHE.HIT",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "References per ICache line that are available
> in the ICache (hit). This event counts differently than Intel processors
> based on Silvermont microarchitecture"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the Instruction Cache
> (ICache) for one or more bytes in an ICache Line and that cache line is not
> in the ICache (miss). The event strives to count on a cache line basis, so
> that multiple accesses which miss in a single cache line count as one
> ICACHE.MISS. Specifically, the event counts when straight line code crosses
> the cache line boundary, or when a branch target is to a new line, and that
> cache line is not in the ICache. This event counts differently than Intel
> processors based on Silvermont microarchitecture.",
> + "EventCode": "0x80",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ICACHE.MISSES",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "References per ICache line that are not
> available in the ICache (miss). This event counts differently than Intel
> processors based on Silvermont microarchitecture"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts requests to the Instruction Cache
> (ICache) for one or more bytes in an ICache Line. The event strives to count
> on a cache line basis, so that multiple fetches to a single cache line count
> as one ICACHE.ACCESS. Specifically, the event counts when accesses from
> straight line code crosses the cache line boundary, or when a branch target
> is to a new line.\r\nThis event counts differently than Intel processors
> based on Silvermont microarchitecture.",
> + "EventCode": "0x80",
> + "Counter": "0,1,2,3",
> + "UMask": "0x3",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ICACHE.ACCESSES",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "References per ICache line. This event counts
> differently than Intel processors based on Silvermont microarchitecture"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of times the Microcode
> Sequencer (MS) starts a flow of uops from the MSROM. It does not count every
> time a uop is read from the MSROM. The most common case that this counts is
> when a micro-coded instruction is encountered by the front end of the
> machine. Other cases include when an instruction encounters a fault, trap,
> or microcode assist of any sort that initiates a flow of uops. The event
> will count MS startups for uops that are speculative, and subsequently
> cleared by branch mispredict or a machine clear.",
> + "EventCode": "0xE7",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MS_DECODED.MS_ENTRY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "MS decode starts"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of times the prediction
> (from the predecode cache) for instruction length is incorrect.",
> + "EventCode": "0xE9",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Decode restrictions due to predicting wrong
> instruction length"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
> b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
> new file mode 100644
> index 0000000..91e0815
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json
> @@ -0,0 +1,38 @@
> +[
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts when a memory load of a uop spans a
> page boundary (a split) is retired.",
> + "EventCode": "0x13",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops that split a page (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts when a memory store of a uop spans a
> page boundary (a split) is retired.",
> + "EventCode": "0x13",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Store uops that split a page (Precise event
> capable)"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts machine clears due to memory ordering
> issues. This occurs when a snoop request happens and the machine is
> uncertain if memory ordering will be preserved - as another core is in the
> process of modifying the data.",
> + "EventCode": "0xC3",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "20003",
> + "BriefDescription": "Machine clears due to memory ordering issue"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
> b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
> new file mode 100644
> index 0000000..b860374
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json
> @@ -0,0 +1,98 @@
> +[
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts cycles that fetch is stalled due to any
> reason. That is, the decoder queue is able to accept bytes, but the fetch
> unit is unable to provide bytes. This will include cycles due to an ITLB
> miss, ICache miss and other events.",
> + "EventCode": "0x86",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "FETCH_STALL.ALL",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Cycles code-fetch stalled due to any reason."
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts cycles that fetch is stalled due to an
> outstanding ITLB miss. That is, the decoder queue is able to accept bytes,
> but the fetch unit is unable to provide bytes due to an ITLB miss. Note:
> this event is not the same as page walk cycles to retrieve an instruction
> translation.",
> + "EventCode": "0x86",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss
> is outstanding."
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of issue slots per core
> cycle that were not consumed by the backend due to either a full resource in
> the backend (RESOURCE_FULL) or due to the processor recovering from some
> event (RECOVERY).",
> + "EventCode": "0xCA",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Unfilled issue slots per cycle"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of issue slots per core
> cycle that were not consumed because of a full resource in the backend.
> Including but not limited to resources such as the Re-order Buffer (ROB),
> reservation stations (RS), load/store buffers, physical registers, or any
> other needed machine resource that is currently unavailable. Note that uops
> must be available for consumption in order for this event to fire. If a uop
> is not available (Instruction Queue is empty), this event will not count.",
> + "EventCode": "0xCA",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Unfilled issue slots per cycle because of a
> full resource in the backend"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of issue slots per core
> cycle that were not consumed by the backend because allocation is stalled
> waiting for a mispredicted jump to retire or other branch-like conditions
> (e.g. the event is relevant during certain microcode flows). Counts all
> issue slots blocked while within this window including slots where uops were
> not available in the Instruction Queue.",
> + "EventCode": "0xCA",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Unfilled issue slots per cycle to recover"
> + },
> + {
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts hardware interrupts received by the
> processor.",
> + "EventCode": "0xCB",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "HW_INTERRUPTS.RECEIVED",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "203",
> + "BriefDescription": "Hardware interrupts received"
> + },
> + {
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts the number of core cycles during which
> interrupts are masked (disabled). Increments by 1 each core cycle that
> EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
> + "EventCode": "0xCB",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "HW_INTERRUPTS.MASKED",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Cycles hardware interrupts are masked"
> + },
> + {
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts core cycles during which there are
> pending interrupts, but interrupts are masked (EFLAGS.IF = 0).",
> + "EventCode": "0xCB",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Cycles pending interrupts are masked"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
> b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
> new file mode 100644
> index 0000000..ccf1aed
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
> @@ -0,0 +1,544 @@
> +[
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of instructions that retire
> execution. For instructions that consist of multiple uops, this event counts
> the retirement of the last uop of the instruction. The counter continues
> counting during hardware interrupts, traps, and inside interrupt handlers.
> This event uses fixed counter 0. You cannot collect a PEBs record for this
> event.",
> + "EventCode": "0x00",
> + "Counter": "Fixed counter 0",
> + "UMask": "0x1",
> + "PEBScounters": "32",
> + "EventName": "INST_RETIRED.ANY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Instructions retired (Fixed event)"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of core cycles while the
> core is not in a halt state. The core enters the halt state when it is
> running the HLT instruction. In mobile systems the core frequency may change
> from time to time. For this reason this event may have a changing ratio with
> regards to time. This event uses fixed counter 1. You cannot collect a PEBs
> record for this event.",
> + "EventCode": "0x00",
> + "Counter": "Fixed counter 1",
> + "UMask": "0x2",
> + "PEBScounters": "33",
> + "EventName": "CPU_CLK_UNHALTED.CORE",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Core cycles when core is not halted (Fixed
> event)"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of reference cycles that the
> core is not in a halt state. The core enters the halt state when it is
> running the HLT instruction. In mobile systems the core frequency may change
> from time. This event is not affected by core frequency changes but counts
> as if the core is running at the maximum frequency all the time. This event
> uses fixed counter 2. You cannot collect a PEBs record for this event.",
> + "EventCode": "0x00",
> + "Counter": "Fixed counter 2",
> + "UMask": "0x3",
> + "PEBScounters": "34",
> + "EventName": "CPU_CLK_UNHALTED.REF_TSC",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Reference cycles when core is not halted
> (Fixed event)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts a load blocked from using a store
> forward, but did not occur because the store data was not available at the
> right time. The forward might occur subsequently when the data is
> available.",
> + "EventCode": "0x03",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "LD_BLOCKS.DATA_UNKNOWN",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Loads blocked due to store data not ready
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts a load blocked from using a store
> forward because of an address/size mismatch, only one of the loads blocked
> from each store will be counted.",
> + "EventCode": "0x03",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "LD_BLOCKS.STORE_FORWARD",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Loads blocked due to store forward restriction
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts loads that block because their address
> modulo 4K matches a pending store.",
> + "EventCode": "0x03",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "LD_BLOCKS.4K_ALIAS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Loads blocked because address has 4k partial
> address false dependence (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts loads blocked because they are unable
> to find their physical address in the micro TLB (UTLB).",
> + "EventCode": "0x03",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "LD_BLOCKS.UTLB_MISS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Loads blocked because address in not in the
> UTLB (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts anytime a load that retires is blocked
> for any reason.",
> + "EventCode": "0x03",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "LD_BLOCKS.ALL_BLOCK",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Loads blocked (Precise event capable)"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts uops issued by the front end and
> allocated into the back end of the machine. This event counts uops that
> retire as well as uops that were speculatively executed but didn't retire.
> The sort of speculative uops that might be counted includes, but is not
> limited to those uops issued in the shadow of a miss-predicted branch, those
> uops that are inserted during an assist (such as for a denormal floating
> point result), and (previously allocated) uops that might be canceled during
> a machine clear.",
> + "EventCode": "0x0E",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "UOPS_ISSUED.ANY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Uops issued to the back end per cycle"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Core cycles when core is not halted. This
> event uses a (_P)rogrammable general purpose performance counter.",
> + "EventCode": "0x3C",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "CPU_CLK_UNHALTED.CORE_P",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Core cycles when core is not halted"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Reference cycles when core is not halted.
> This event uses a (_P)rogrammable general purpose performance counter.",
> + "EventCode": "0x3C",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "CPU_CLK_UNHALTED.REF",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Reference cycles when core is not halted"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "This event used to measure front-end
> inefficiencies. I.e. when front-end of the machine is not delivering uops to
> the back-end and the back-end has is not stalled. This event can be used to
> identify if the machine is truly front-end bound. When this event occurs, it
> is an indication that the front-end of the machine is operating at less than
> its theoretical peak performance. Background: We can think of the processor
> pipeline as being divided into 2 broader parts: Front-end and Back-end.
> Front-end is responsible for fetching the instruction, decoding into uops in
> machine understandable format and putting them into a uop queue to be
> consumed by back end. The back-end then takes these uops, allocates the
> required resources. When all resources are ready, uops are executed. If the
> back-end is not ready to accept uops from the front-end, then we do not want
> to count these as front-end bottlenecks. However, whenever we have
> bottlenecks in the back-end, we w
> ill have allocation unit stalls and eventually forcing the front-end to wait
> until the back-end is ready to receive more uops. This event counts only when
> back-end is requesting more uops and front-end is not able to provide them.
> When 3 uops are requested and no uops are delivered, the event counts 3. When
> 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are
> delivered, the event counts 1. Alternatively stated, the event will not count
> if 3 uops are delivered, or if the back end is stalled and not requesting any
> uops at all. Counts indicate missed opportunities for the front-end to
> deliver a uop to the back end. Some examples of conditions that cause
> front-end efficiencies are: ICache misses, ITLB misses, and decoder
> restrictions that limit the front-end bandwidth. Known Issues: Some uops
> require multiple allocation slots. These uops will not be charged as a front
> end 'not delivered' opportunity, and will be regarded as a back end problem.
> For example, the
> INC instruction has one uop that requires 2 issue slots. A stream of INC
> instructions will not count as UOPS_NOT_DELIVERED, even though only one
> instruction can be issued per clock. The low uop issue rate for a stream of
> INC instructions is considered to be a back end issue.",
> + "EventCode": "0x9C",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "UOPS_NOT_DELIVERED.ANY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Uops requested but not-delivered to the
> back-end per cycle"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of instructions that retire
> execution. For instructions that consist of multiple uops, this event counts
> the retirement of the last uop of the instruction. The event continues
> counting during hardware interrupts, traps, and inside interrupt handlers.
> This is an architectural performance event. This event uses a
> (_P)rogrammable general purpose performance counter. *This event is Precise
> Event capable: The EventingRIP field in the PEBS record is precise to the
> address of the instruction which caused the event. Note: Because PEBS
> records can be collected only on IA32_PMC0, only one event can use the PEBS
> facility at a time.",
> + "EventCode": "0xC0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "INST_RETIRED.ANY_P",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Instructions retired (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Skid
> PEBS feature that reduces the shadow in which events aren't counted allowing
> for a more unbiased distribution of samples across instructions retired.",
> + "EventCode": "0xC0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "EventName": "INST_RETIRED.PREC_DIST",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Instructions retired - using Reduced Skid PEBS
> feature"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts uops which retired.",
> + "EventCode": "0xC2",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "UOPS_RETIRED.ANY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Uops retired (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts uops retired that are from the complex
> flows issued by the micro-sequencer (MS). Counts both the uops from a
> micro-coded instruction, and the uops that might be generated from a
> micro-coded assist.",
> + "EventCode": "0xC2",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "UOPS_RETIRED.MS",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "MS uops retired (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of floating point divide
> uops retired.",
> + "EventCode": "0xC2",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "UOPS_RETIRED.FPDIV",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Floating point divide uops retired (Precise
> Event Capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of integer divide uops
> retired.",
> + "EventCode": "0xC2",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "UOPS_RETIRED.IDIV",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Integer divide uops retired (Precise Event
> Capable)"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts machine clears for any reason.",
> + "EventCode": "0xC3",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MACHINE_CLEARS.ALL",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "20003",
> + "BriefDescription": "All machine clears"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of times that the processor
> detects that a program is writing to a code section and has to perform a
> machine clear because of that modification. Self-modifying code (SMC) causes
> a severe penalty in all Intel architecture processors.",
> + "EventCode": "0xC3",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MACHINE_CLEARS.SMC",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "20003",
> + "BriefDescription": "Self-Modifying Code detected"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts machine clears due to floating point
> (FP) operations needing assists. For instance, if the result was a floating
> point denormal, the hardware clears the pipeline and reissues uops to produce
> the correct IEEE compliant denormal result.",
> + "EventCode": "0xC3",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MACHINE_CLEARS.FP_ASSIST",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "20003",
> + "BriefDescription": "Machine clears due to FP assists"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts machine clears due to memory
> disambiguation. Memory disambiguation happens when a load which has been
> issued conflicts with a previous unretired store in the pipeline whose
> address was not known at issue time, but is later resolved to be the same as
> the load address.",
> + "EventCode": "0xC3",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MACHINE_CLEARS.DISAMBIGUATION",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "20003",
> + "BriefDescription": "Machine clears due to memory disambiguation"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of times that the machines
> clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page
> faults. A page fault occurs when either page is not present, or an access
> violation",
> + "EventCode": "0xC3",
> + "Counter": "0,1,2,3",
> + "UMask": "0x20",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MACHINE_CLEARS.PAGE_FAULT",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "20003",
> + "BriefDescription": "Machines clear due to a page fault"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts branch instructions retired for all
> branch types. This is an architectural performance event.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired branch instructions (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts retired Jcc (Jump on Conditional
> Code/Jump if Condition is Met) branch instructions retired, including both
> when the branch was taken and when it was not taken.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0x7e",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.JCC",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired conditional branch instructions
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts the number of taken branch instructions
> retired.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0x80",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired taken branch instructions (Precise
> event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts far branch instructions retired. This
> includes far jump, far call and return, and Interrupt call and return.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0xbf",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.FAR_BRANCH",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired far branch instructions (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts near indirect call or near indirect jmp
> branch instructions retired.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0xeb",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.NON_RETURN_IND",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired instructions of near indirect Jmp or
> call (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts near return branch instructions
> retired.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0xf7",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.RETURN",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired near return instructions (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts near CALL branch instructions retired.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0xf9",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.CALL",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired near call instructions (Precise event
> capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts near indirect CALL branch instructions
> retired.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0xfb",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.IND_CALL",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired near indirect call instructions
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts near relative CALL branch instructions
> retired.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0xfd",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.REL_CALL",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired near relative call instructions
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if
> Condition is Met) branch instructions retired that were taken and does not
> count when the Jcc branch instruction were not taken.",
> + "EventCode": "0xC4",
> + "Counter": "0,1,2,3",
> + "UMask": "0xfe",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_INST_RETIRED.TAKEN_JCC",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired conditional branch instructions that
> were taken (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts mispredicted branch instructions
> retired including all branch types.",
> + "EventCode": "0xC5",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired mispredicted branch instructions
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts mispredicted retired Jcc (Jump on
> Conditional Code/Jump if Condition is Met) branch instructions retired,
> including both when the branch was supposed to be taken and when it was not
> supposed to be taken (but the processor predicted the opposite condition).",
> + "EventCode": "0xC5",
> + "Counter": "0,1,2,3",
> + "UMask": "0x7e",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_MISP_RETIRED.JCC",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired mispredicted conditional branch
> instructions (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts mispredicted branch instructions
> retired that were near indirect call or near indirect jmp, where the target
> address taken was not what the processor predicted.",
> + "EventCode": "0xC5",
> + "Counter": "0,1,2,3",
> + "UMask": "0xeb",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired mispredicted instructions of near
> indirect Jmp or near indirect call (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts mispredicted near RET branch
> instructions retired, where the return address taken was not what the
> processor predicted.",
> + "EventCode": "0xC5",
> + "Counter": "0,1,2,3",
> + "UMask": "0xf7",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_MISP_RETIRED.RETURN",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired mispredicted near return instructions
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts mispredicted near indirect CALL branch
> instructions retired, where the target address taken was not what the
> processor predicted.",
> + "EventCode": "0xC5",
> + "Counter": "0,1,2,3",
> + "UMask": "0xfb",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_MISP_RETIRED.IND_CALL",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired mispredicted near indirect call
> instructions (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts mispredicted retired Jcc (Jump on
> Conditional Code/Jump if Condition is Met) branch instructions retired that
> were supposed to be taken but the processor predicted that it would not be
> taken.",
> + "EventCode": "0xC5",
> + "Counter": "0,1,2,3",
> + "UMask": "0xfe",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BR_MISP_RETIRED.TAKEN_JCC",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Retired mispredicted conditional branch
> instructions that were taken (Precise event capable)"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts core cycles if either divide unit is
> busy.",
> + "EventCode": "0xCD",
> + "Counter": "0,1,2,3",
> + "UMask": "0x0",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "CYCLES_DIV_BUSY.ALL",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Cycles a divider is busy"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts core cycles the integer divide unit is
> busy.",
> + "EventCode": "0xCD",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "CYCLES_DIV_BUSY.IDIV",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Cycles the integer divide unit is busy"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts core cycles the floating point divide
> unit is busy.",
> + "EventCode": "0xCD",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "CYCLES_DIV_BUSY.FPDIV",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Cycles the FP divide unit is busy"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of times a BACLEAR is
> signaled for any reason, including, but not limited to indirect branch/call,
> Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional
> branch/call, and returns.",
> + "EventCode": "0xE6",
> + "Counter": "0,1,2,3",
> + "UMask": "0x1",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BACLEARS.ALL",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "BACLEARs asserted for any branch type"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts BACLEARS on return instructions.",
> + "EventCode": "0xE6",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BACLEARS.RETURN",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "BACLEARs asserted for return branch"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional
> Code/Jump if Condition is Met) branches.",
> + "EventCode": "0xE6",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "BACLEARS.COND",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "BACLEARs asserted for conditional branch"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
> b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
> new file mode 100644
> index 0000000..0b53a3b
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
> @@ -0,0 +1,218 @@
> +[
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to demand data
> loads (including SW prefetches) whose address translations missed in all TLB
> levels and were mapped to 4K pages. The page walks can end with or without a
> page fault.",
> + "EventCode": "0x08",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Page walk completed due to a demand load to a
> 4K page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to demand data
> loads (including SW prefetches) whose address translations missed in all TLB
> levels and were mapped to 2M or 4M pages. The page walks can end with or
> without a page fault.",
> + "EventCode": "0x08",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Page walk completed due to a demand load to a
> 2M or 4M page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to demand data
> loads (including SW prefetches) whose address translations missed in all TLB
> levels and were mapped to 1GB pages. The page walks can end with or without
> a page fault.",
> + "EventCode": "0x08",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Page walk completed due to a demand load to a
> 1GB page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts once per cycle for each page walk
> occurring due to a load (demand data loads or SW prefetches). Includes cycles
> spent traversing the Extended Page Table (EPT). Average cycles per walk can
> be calculated by dividing by the number of walks.",
> + "EventCode": "0x08",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Page walks outstanding due to a demand load
> every cycle."
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to demand data
> stores whose address translations missed in the TLB and were mapped to 4K
> pages. The page walks can end with or without a page fault.",
> + "EventCode": "0x49",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Page walk completed due to a demand data store
> to a 4K page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to demand data
> stores whose address translations missed in the TLB and were mapped to 2M or
> 4M pages. The page walks can end with or without a page fault.",
> + "EventCode": "0x49",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Page walk completed due to a demand data store
> to a 2M or 4M page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to demand data
> stores whose address translations missed in the TLB and were mapped to 1GB
> pages. The page walks can end with or without a page fault.",
> + "EventCode": "0x49",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Page walk completed due to a demand data store
> to a 1GB page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts once per cycle for each page walk
> occurring due to a demand data store. Includes cycles spent traversing the
> Extended Page Table (EPT). Average cycles per walk can be calculated by
> dividing by the number of walks.",
> + "EventCode": "0x49",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Page walks outstanding due to a demand data
> store every cycle."
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts once per cycle for each page walk only
> while traversing the Extended Page Table (EPT), and does not count during the
> rest of the translation. The EPT is used for translating Guest-Physical
> Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average
> cycles per walk can be calculated by dividing the count by number of walks.",
> + "EventCode": "0x4F",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "EPT.WALK_PENDING",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Page walks outstanding due to walking the EPT
> every cycle"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts the number of times the machine was
> unable to find a translation in the Instruction Translation Lookaside Buffer
> (ITLB) for a linear address of an instruction fetch. It counts when new
> translation are filled into the ITLB. The event is speculative in nature,
> but will not count translations (page walks) that are begun and not finished,
> or translations that are finished but not filled into the ITLB.",
> + "EventCode": "0x81",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ITLB.MISS",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "ITLB misses"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to instruction
> fetches whose address translations missed in the TLB and were mapped to 4K
> pages. The page walks can end with or without a page fault.",
> + "EventCode": "0x85",
> + "Counter": "0,1,2,3",
> + "UMask": "0x2",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Page walk completed due to an instruction fetch
> in a 4K page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to instruction
> fetches whose address translations missed in the TLB and were mapped to 2M or
> 4M pages. The page walks can end with or without a page fault.",
> + "EventCode": "0x85",
> + "Counter": "0,1,2,3",
> + "UMask": "0x4",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Page walk completed due to an instruction fetch
> in a 2M or 4M page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts page walks completed due to instruction
> fetches whose address translations missed in the TLB and were mapped to 1GB
> pages. The page walks can end with or without a page fault.",
> + "EventCode": "0x85",
> + "Counter": "0,1,2,3",
> + "UMask": "0x8",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "2000003",
> + "BriefDescription": "Page walk completed due to an instruction fetch
> in a 1GB page"
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts once per cycle for each page walk
> occurring due to an instruction fetch. Includes cycles spent traversing the
> Extended Page Table (EPT). Average cycles per walk can be calculated by
> dividing by the number of walks.",
> + "EventCode": "0x85",
> + "Counter": "0,1,2,3",
> + "UMask": "0x10",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "ITLB_MISSES.WALK_PENDING",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Page walks outstanding due to an instruction
> fetch every cycle."
> + },
> + {
> + "CollectPEBSRecord": "1",
> + "PublicDescription": "Counts STLB flushes. The TLBs are flushed on
> instructions like INVLPG and MOV to CR3.",
> + "EventCode": "0xBD",
> + "Counter": "0,1,2,3",
> + "UMask": "0x20",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "TLB_FLUSHES.STLB_ANY",
> + "PDIR_COUNTER": "na",
> + "SampleAfterValue": "20003",
> + "BriefDescription": "STLB flushes"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts load uops retired that caused a DTLB
> miss.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x11",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Load uops retired that missed the DTLB (Precise
> event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts store uops retired that caused a DTLB
> miss.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x12",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Store uops retired that missed the DTLB
> (Precise event capable)"
> + },
> + {
> + "PEBS": "2",
> + "CollectPEBSRecord": "2",
> + "PublicDescription": "Counts uops retired that had a DTLB miss on
> load, store or either. Note that when two distinct memory operations to the
> same page miss the DTLB, only one of them will be recorded as a DTLB miss.",
> + "EventCode": "0xD0",
> + "Counter": "0,1,2,3",
> + "UMask": "0x13",
> + "PEBScounters": "0,1,2,3",
> + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
> + "SampleAfterValue": "200003",
> + "BriefDescription": "Memory uops retired that missed the DTLB
> (Precise event capable)"
> + }
> +]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv
> b/tools/perf/pmu-events/arch/x86/mapfile.csv
> index 4ea0683..fe1a2c4 100644
> --- a/tools/perf/pmu-events/arch/x86/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
> @@ -9,6 +9,7 @@ GenuineIntel-6-27,v4,bonnell,core
> GenuineIntel-6-36,v4,bonnell,core
> GenuineIntel-6-35,v4,bonnell,core
> GenuineIntel-6-5C,v8,goldmont,core
> +GenuineIntel-6-7A,v1,goldmontplus,core
> GenuineIntel-6-3C,v24,haswell,core
> GenuineIntel-6-45,v24,haswell,core
> GenuineIntel-6-46,v24,haswell,core
> --
> 2.7.4
