Our CR4-based TLB flush currently requries global pages to be
supported *and* enabled. But, we really only need for them to be
supported. Make the code more robust by alllowing X86_CR4_PGE to
clear as well as set.
This change was suggested by Kirill Shutemov.
Signed-off-by: Dave Hansen <dave.han...@linux.intel.com>
Cc: Moritz Lipp <moritz.l...@iaik.tugraz.at>
Cc: Daniel Gruss <daniel.gr...@iaik.tugraz.at>
Cc: Michael Schwarz <michael.schw...@iaik.tugraz.at>
Cc: Andy Lutomirski <l...@kernel.org>
Cc: Linus Torvalds <torva...@linux-foundation.org>
Cc: Kees Cook <keesc...@google.com>
Cc: Hugh Dickins <hu...@google.com>
Cc: x...@kernel.org
---
b/arch/x86/include/asm/tlbflush.h | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff -puN
arch/x86/include/asm/tlbflush.h~kaiser-prep-make-cr4-writes-tolerate-clear-pge
arch/x86/include/asm/tlbflush.h
---
a/arch/x86/include/asm/tlbflush.h~kaiser-prep-make-cr4-writes-tolerate-clear-pge
2017-10-31 15:03:49.913092716 -0700
+++ b/arch/x86/include/asm/tlbflush.h 2017-10-31 15:03:49.917092905 -0700
@@ -250,9 +250,20 @@ static inline void __native_flush_tlb_gl
unsigned long cr4;
cr4 = this_cpu_read(cpu_tlbstate.cr4);
- /* clear PGE */
- native_write_cr4(cr4 & ~X86_CR4_PGE);
- /* write old PGE again and flush TLBs */
+ /*
+ * This function is only called on systems that support X86_CR4_PGE
+ * and where always set X86_CR4_PGE. Warn if we are called without
+ * PGE set.
+ */
+ WARN_ON_ONCE(!(cr4 & X86_CR4_PGE));
+ /*
+ * Architecturally, any _change_ to X86_CR4_PGE will fully flush the
+ * TLB of all entries including all entries in all PCIDs and all
+ * global pages. Make sure that we _change_ the bit, regardless of
+ * whether we had X86_CR4_PGE set in the first place.
+ */
+ native_write_cr4(cr4 ^ X86_CR4_PGE);
+ /* Put original CR3 value back: */
native_write_cr4(cr4);
}
_
