On Tue, Nov 21, 2017 at 10:57 AM, Dave Hansen <[email protected]> wrote: > On 11/20/2017 09:07 AM, Andy Lutomirski wrote: >> --- a/arch/x86/entry/entry_64.S >> +++ b/arch/x86/entry/entry_64.S >> @@ -560,6 +560,14 @@ END(irq_entries_start) >> .macro interrupt func >> cld >> ALLOC_PT_GPREGS_ON_STACK >> + >> + testb $3, CS(%rsp) >> + jz 1f >> + SWAPGS >> + call switch_to_thread_stack >> + SWAPGS >> +1: > > This looks really weird to me. SWAPGS, switch stack, and SWAPGS again? > > Is this so that we can use some per-cpu data in switch_to_thread_stack, > and then put GS back so that the normal, non-trampoline entry code can > do its normal SWAPGS voodoo? > >
Yes. I was trying to avoid totally restructuring error_entry here.
