* Dave Hansen <dave.han...@linux.intel.com> wrote:
> On 11/23/2017 10:35 PM, Ingo Molnar wrote:
> > So the pteval_t changes break the build on most non-x86 architectures
> > (alpha, arm,
> > arm64, etc.), because most of them don't have an asm/pgtable_types.h file.
> >
> > pteval_t is an x86-ism.
> >
> > So I left out the changes below.
>
> There was a warning on the non-PAE 32-bit builds saying that there was a
> shift larger than the type. I assumed this was because of a reference
> to _PAGE_NX, and thus we needed a change to pteval_t.
>
> But, now that I think about it more, that doesn't make sense since
> _PAGE_NX should be #defined down to a 0 on those configs unless
> something is wrong.
If pte flags need to be passed around then the canonical way to do it is to
pass
around a pte_t, and use pte_val() on it and such.
But please investigate the warning.
One other detail: I see you fixed some of the commit titles to use standard x86
tags - could you please also capitalize sentences? I.e.:
- x86/mm/kaiser: allow flushing for future ASID switches
+ x86/mm/kaiser: Allow flushing for future ASID switches
Could you please also double-check whether the merges I did in the latest
WIP.x86/mm branch are OK? Andy changed the entry stack code a bit under Kaiser,
which created about 3 new conflicts.
The key resolutions that I did were:
.macro interrupt func
cld
testb $3, CS-ORIG_RAX(%rsp)
jz 1f
SWAPGS
SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
call switch_to_thread_stack
1:
Plus I also dropped the extra switch_to_thread_stack call done in:
x86/mm/kaiser: Prepare assembly for entry/exit CR3 switching
Because Andy's latest preparatory patch does it now:
x86/entry/64: Use a percpu trampoline stack for IDT entries
Thanks,
Ingo
